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ALU 31 I-type (immediate) op 31 J-type(jarap> 31 op 26 25 op rs 21 20 rt 16 15 rd 26 25 26 25 rs 2120 rt 16 15 immediate
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R-type (register)
Implementation of Pipeline Interlock for Hazards Involving a Branch Instruction
Instruction Formats Used in the M I P S Instruction Set Architecture
M O D E R N PROCESSOR DESIGN
PIPELINED P R O C E S S O R S
Instructions can be divided into four types Computational instructions perform arithmetic, logical, and shift operations on register operands They can employ the R-type format if all the operands and the result are registers, or the I-rype format if one of the operands is specified in the immediate field of the instruction
Load/store instructions move data between the memory and registers They employ the I-type format The only addressing mode is the base register plus the signed offset stored in the immediate field Jump and branch instructions steer the control flow of the program Jumps are unconditional and use the J-type format to jump to an absolute address composed of the 26-bit target and the high-order 4 bits of the PC Branches are conditional and use the I-type format to specify the target address as the PC plus the 16-bit offset in the immediate field Other instructions in the instruction set are used to perform operations in the coprocessors and other special system functions Coprocessor 0 (CPU) is the system control coprocessor CPO instructions manipulate the memory management and exception handling facilities Floating-point instructions are implemented as coprocessor instructions and are performed by a separate floating-point processor
The MIPS R2000/R3000 pipeline is a five-stage instruction pipeline quite similar to the T Y P pipeline However, each pipeline stage is further divided into two separate phases, identified as phase one (0 1) and phase two (<|>2) The functions performed by each of the five stages and their phases are described in Table 27 There are a number of interesting features in this five-stage pipeline The I-cache access, which requires an entire cycle, actually takes place during 02 of
Table 27 Functionality of the MIPS R2000/R3000 five-stage pipeline Stage Name
1 IF
Phase
01 02
Function Performed
Translate virtual instruction address using TLB Access I-cache using physical address Return instructions from I-cache; check tags and parity Read register file; if a branch, generate target address Start A L U operation; if a branch, check branch condition Finish A L U operation; if a load/store, translate virtual address
2RD
01 02
the IF stage and 01 of the RD stage One translation lookaside buffer (TLB) is nsed to do address translation for both the I-cache and the D-cache The TLB is accessed during 0 1 of the IF stage, for supporting I-cache access and is accessed during <]>2 of the ALU stage, for supporting D-cache access, which takes place during the M E M cycle The register file performs first a write (0 1 of WB stage), and then a read (<|>2 of RD stage) in every machine cycle This pipeline requires a three-ported (two reads and one write) register file and a single-ported I-cache and a single-ported D-cache to support the IF and MEM stages, respectively With forwarding paths from the outputs of the ALU and the MEM stages back to the input of the ALU stage, no ALU leading hazards will incur a penalty cycle The load penalty, that is, the worst-case penalty incurred by a load leading hazard, is only one cycle with the forwarding path from the output of the MEM stage to the input of the ALU stage The branch penalty is also only one cycle This is made possible due to several features of the R2O00/R3O00 pipeline First, branch instructions use only PC-relative addressing mode Unlike a register which must be accessed during the RD stage, the PC is available after the IF stage Hence, the branch target address can be calculated, albeit using a separate adder, during the RD stage The second feature is that no explicit condition code bit is generated and stored The branch condition is generated during <|>1 of the ALU stage by comparing the contents of the referenced register(s) Normally with the branch condition being generated in the ALU stage (stage 3) and the instruction fetch being done in the IF stage (stage 1), the expected penalty would be two cycles However, in this particular pipeline design the I-cache access actually does not start until 02 of the IF stage With the branch condition being available at the end of < 1 of the > | ALU stage and since the I-cache access does not begin until 02 of the IF stage, the branch target address produced at the end of the RD stage can be steered by the branch condition into the PC prior to the start of I-cache access in the middle of the IF stage Consequendy only a one-cycle penalty is incurred by branch instructions Compared to the six-stage TYP pipeline, the five-stage MIPS R20O0/R3O00 pipeline is a better design in terms of the penalties incurred due to pipeline hazards Both pipelines have the same ALU and load penalties of zero cycles and one cycle, respectively However, due to the above stated features in its design, the MIPS R2000/R3000 pipeline incurs only one cycle, instead of four cycles, for its branch penalty Influenced by and having benefited from the RISC research done at Stanford University, the MIPS R2O00/R3O00 has a very clean design and is a highly efficient pipelined processor 2242 CISC Pipelined Processor Example In 1978 Intel introduced one of the first 16-bit microprocessors, the Intel 8086 Although preceded by earlier 8-bit microprocessors from Intel (8080 and 8085), the 8086 began an evolution that would eventually result in the Intel IA32 family of object code compatible microprocessors The Intel IA32 is a CISC architecture with variable-length instructions a n d ' complex addressing modes, and it is by far the most dominant architecture today in terms of sales volume and the accompanying application software base In 1985, the Intel 386, the 32-bit version of the IA32 family, was introduced [Crawford, 1986] The first pipelined version of the IA32 family, the Intel 486, was introduced in 1989
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