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Physical execution with software instrumentation Physical execution with hardware instrumentation Trace storage Functional simulator Trace generation
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Performance Simulation M e t h o d s : (a) Trace-Driven Simulation; (b) Execution-Driven Simulation
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j which inserts special instructions into a program prior to run time so that when the Vy instrumented program is executed on a physical system, the inserted instructions will produce the dynamic execution trace Another way is via hardware instrumentation, which involves putting special hardware probes to monitor the system bus and to record the actual execution trace when a program is executed on the system Software instrumentation can significantly increase the code size and the program execution time Hardware instrumentation requires the monitoring hardware and is seriously limited by the buffering capacity of the monitoring hardware The third trace generation method uses a functional simulator to simulate the execution of a program During simulation, hooks are embedded in the simulator to record the dynamic execution trace For all three methods, once traces are generated, they caa be stored for subsequent repeated use by trace-driven performance simulators ExecijtiQn^djjxenj^ormance simulators overcome some of the limitations of trace-driven performance simulators; see Figure 14(b) Instead of using pregenerated traces, an execution-driven performanc^imulator is interfaced to a functional simulator, and the two simulators work in tandem During simulation, the functional simulator executes the instructions and passes information associated with the executed instructions to the performance simulator The performance simulator then tracks the timing of these instructions and their movement through the pipeline stages It has fhejjbililyjoisjsue directives to thp, fiinctionaljjirniilatnr to checkpoint the simulation state and toJateiresumeJronithe_checkpointed state The checkpoint capability allows the simulation, of speculative instructions, such as instructions
following a branch prediction More specifically, execution-driven simulation can simulate the mis-speculated instructions, such as the instructions following a mispredicted branch, going through the pipeline In trace-driven simulation, the pregenerated trace contains only the actual (nonspeculative) instructions executed, and a trace-driven simulator cannot account for the instructions on a mis-speculated path and their potential contention for resources with other (nonspeculative) instructions Execution-driven simulators also alleviate the need to store long traces Most modern performance simulators employ the execution-driven paradigm The most advanced execution-driven performance simulators are supported by functional simulators that are capable of performing full-system simulation, that is, the simulation of both application and operating system instructions, the memory hierarchy, jmd even input/output devices The actual implementation of the microarchitecture model in a performance simulator can vary widely in terms of the amount and details of machine resources that are explicitly modeled Some performance models are merely cycle counters that assume unlimited resources and simply calculate the total number of cycles needed for the execution of a trace, taking into account inter-instruction dependences Others explicitly model the organization of the machine with all its component modules These performance models actually simulate the movement of instructions through the various pipeline stages, including the allocation of limited machine resources in each machine cycle While many performance simulators claim to be "cycle-accurate," the methods they use to model and track the activities in each machine cycle can be quite different While there is heavy reliance on performance simulators during the early design stages of a microprocessor, the validation of the accuracy of performance simulators is an extremely difficult task Typically the performance model or simulator is implemented in the early phase of the design and is used to do initial tradeoffs of various microarchitecture features During this phase there isn't a reference that can be used to validate the performance model As_the-design-progresscs and an RTL rnpdelof the design is deyeloped^the RTL model can beused-asAffit erencejoj5lidateJhe_accjffiacy of theperfbrmance model However,, simulation using the RTL model is very slow^ and tnereTorTonlyrvery short traees-can-boused During the entire design process, discipline is essential to concurrently evolve the performance model and the RTL model to ensure that the performance model is tracking all the changes made in the RTL model It is also important to do post-silicon validation of the performance model so that it can be used as a good starting point for the next-generation design Most performance simulators used in academic research are never validated These simulators can be quite complex and, just like all large pieces of software, can contain many bugs that are difficult to eliminate It is quite likely that a large fraction of the performance data published in many research papers using unvalidated performance models is completely erroneous Black argues convincingly for more rigorous validation of processor simulators [Black and Shen, 1998] Other than the difficulty of validating their accuracy, another problem associated with performance simulators is the extremely long simulation times that are often
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