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98 Repeat the analysis of Example 97 for RS = 400 in What is the collector current
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99 What is the power dissipated by the LED of Example 97 if RS = 30
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The second transistor family discussed in this chapter operates on the basis of a principle that is quite different from that of the pn junction devices The concept that forms the basis of the operation of the eld-effect transistor, or FET, is that the width of a conducting channel in a semiconductor may be varied by the external application of an electric eld Thus, FETs behave as voltage-controlled resistors This family of electronic devices can be subdivided into three groups, all of which will be introduced in the remainder of this chapter Figure 928 depicts the classi cation of eld-effect transistors, as well as the more commonly used symbols for these devices These devices can be grouped into three major categories The rst two categories are both types of metal-oxide-semiconductor eld-effect transistors, or MOSFETs: enhancement-mode MOSFETs and depletion-mode MOSFETs The third category consists of junction eld-effect transistors, or JFETs In addition, each of these devices can be fabricated either as an n-channel device or as a p-channel device, where the n or p designation indicates the nature of the doping in the semiconductor channel All these transistors behave in a very similar fashion, and we shall predominantly discuss enhancement MOSFETs in this chapter, although some discussion of depletion devices and JFETs will also be included
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n-channel
Depletion MOS
p-channel
n-channel JFET
p-channel
n-channel
Figure 928 Classi cation of eld-effect transistors
OVERVIEW OF ENHANCEMENT-MODE MOSFETS
Gate Source n+ p Bulk (substrate) Drain n+
Figure 929 depicts the circuit symbol and the approximate construction of a typical n-channel enhancement-mode MOSFET The device has three terminals: the gate (analogous to the base in a BJT); the drain (analogous to the collector); and the source (analogous to the emitter) The bulk or substrate of the device is shown to be electrically connected to the source, and therefore does not appear in the electrical circuit diagram as a separate terminal The gate consists of a metal lm layer, separated from the p-type bulk by a thin oxide layer (hence the terminology metal-oxide-semiconductor) The drain and source are both constructed of n+ material Imagine now that the drain is connected to a positive voltage supply, VDD , and the source is connected to ground Since the p-type bulk is connected to the source, and hence to ground, the drain-bulk n+ p junction is strongly reversebiased The junction voltage for the pn+ junction formed by the bulk and the source is zero, since both are connected to ground Thus, the path between drain and source consists of two reverse-biased p-n junctions, and no current can ow This situation is depicted in Figure 930(a): in the absence of a gate voltage, the nchannel enhancement-mode MOSFET acts as an open circuit Thus, enhancementmode devices are normally off Suppose now that a positive voltage is applied to the gate; this voltage will create an electric eld in the direction shown in Figure 930(b) The effect of the electric eld is to repel positive charge carriers away from the surface of the p-type bulk, and to form a narrow channel near the surface of the bulk in which negative charge carriers dominate, and are available for conduction For a xed drain bias, the greater the strength of the externally applied electric eld (that is, the higher the gate voltage), the deeper the channel This behavior explains the terminology enhancement-mode, because the application of an external electric eld enhances the conduction in the channel by creating n-type charge carriers It should also be
D iD + VDS _ G +V GS _ S
Figure 929 n-channel enhancement MOSFET construction and circuit symbol
9
Transistor Fundamentals
+ VDS _
Gate Source
+ V _ DD
Drain p Bulk (substrate) n+
+ V _ DD
+ VDS _
Gate
VGG +_
+ V _ DD
Source + + + + + + + + + + + + Drain n n+ n+ Channel p Bulk (substrate)
+ V _ DD
S VGG
G + + VGS S _ _
An n-channel MOSFET is normally off in the absence of an external electric field
When a gate voltage is applied, a conducting n-type channel is formed near the surface of the substrate; now current can flow from drain to source
+ VDS _
+ VDS _
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