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Encoder QR-Code in Software Part II

Part II
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EXAMPLE 911 Determining the Operating Region of a JFET
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Problem
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Determine the operating region of each of the JFETs in Figure 942
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VDD = 15 V 500 iD
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VDD = 15 V iD 145 k
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Known Quantities: Drain resistance; JFET parameters IDSS and VP Find: Operating region of each JFET
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+ vDS + vDS
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RD(b) = 145 k ; VP = 4 V; IDSS = 10 mA
Schematics, Diagrams, Circuits, and Given Data: VDD = 15 V; RD(a) = 500 Assumptions: Use the JFET equations of Table 92 Analysis:
1 Circuit (a) Since vGS = 0, we know (by de nition) that iD = IDSS = 10 mA We can therefore write the drain circuit equation: VDD = RD iD + vDS and calculate vDS = VDD RD iD = 15 500 10 2 = 10 V From Table 92, we see that the condition for operation in the saturation region is vDS > VGS + VP Since 10 > 0 + 4, we conclude that the JFET of circuit (a) is operating in the active region 2 Circuit (b) The drain circuit equation is: VDD = RD iD + vDS and vDS = VDD RD iD = 15 145 103 10 2 = 05 V From Table 92, we see that the condition for operation in the saturation region is vDS > vGS + VP , but in this case, 05 < 0 + 4, and we therefore conclude that the JFET is in the ohmic region We can also directly check the condition for ohmic operation given in Table 92: |vDS | < 025(vGS + VP ) and con rm that, indeed, the JFET operates in the ohmic region since 05 < 1
EXAMPLE 912 Biasing a JFET
Problem
Design the JFET bias circuit of Figure 943 to operate in the saturation region with a drain current of 4 mA and a drain-source voltage of 10 V
9
Transistor Fundamentals
VDD RD + vDS RG RS
Solution
Known Quantities: Drain resistance; JFET parameters IDSS and VP ; JFET breakdown
voltage
Find: Drain, gate and source resistances, drain supply voltage
+ VG
mA; VB = 30 V
Schematics, Diagrams, Circuits, and Given Data: VP = 3 V; IDSS = 6 mA; iDQ = 4 Assumptions: Use the JFET equations of Table 92
Analysis: The information regarding the breakdown voltage, VB , is useful to select the drain supply voltage The drain supply must be less than the breakdown voltage to prevent device failure; VDD = 24 V is a reasonable choice The resistance RG serves the purpose of tying the gate to ground This is usually accomplished with a large resistance Any leakage current would be only of the order of nanoamperes, so the gate would be at most a few mV above ground Let s choose RG = 1 M Using the universal equation for the saturation region from Table 92, we write:
iD =
IDSS (vGS + VP )2 = IDSS 2 VP
vGS +1 VP
Knowing the desired drain current, we can expand the above equation to obtain: IDSS 2 IDSS v +2 vGS + 2 iDQ VP iDQ VP GS IDSS 1 =0 iDQ
2 0166vGS + vGS + 05 = 0
with roots vGS = 545V vGS = 055V
Since the JFET is in the active region only if vGS > VP , the only acceptable solution is vGSQ = 055 V To obtain the desired value of vGSQ we must choose an appropriate value of RS Remember that we know the value of the quiescent drain current (we desire 4 mA) Thus, we desire vGSQ = vG vS = 055 V, and since vG = 0: vS = 055 = iDQ RS or RS = 055 = 1375 0004
Now we can write the drain circuit equation to determine the appropriate value of RD to ensure that vDS = 10 V: VDD = RD iD + vDS + RS iD or 24 = 0004RD + 10 + 055 from which equation RD can be computed to be approximately 336 k
Part II
Electronics
Comments: The value of source and drain resistance computed in the above example are not standard resistor values (see 2, Table 21); engineering practice would require that the nearest available standard values be used: RS = 150 , RD = 333 k
EXAMPLE 913 JFET Current Source
Problem
VDD ID RL RL VDD
Show that the circuit of Figure 944 can act as a current source
Solution
Known Quantities: Drain and source resistance; JFET parameters IDSS and VP ; Drain
ID RS
supply voltage
Find: Explain why the circuit of Figure 944(a) can be modeled by the circuit of Figure
944(b)
Schematics, Diagrams, Circuits, and Given Data: VP = 3 V; IDSS = 6 mA; RS = 1 k Assumptions: Use the JFET equations of Table 92 Analysis: We have already seen in Example 912 that a JFET can be biased in the
saturation region with vG = 0 The simple circuit shown in Figure 944(a) can therefore be biased in the saturation region provided that vDS > vGS + VP (see Table 92) Note that if the source resistor, RS , were set equal to zero, then we would have vGS = 0, and the saturation region equation from Table 92 would simplify to iD = IDSS Thus, any JFET can be operated as a current source with iD = IDSS simply by tying the gate and source to ground Unfortunately, because of the uncertainties in the fabrication process, the parameter IDSS can vary signi cantly even among nominally identical transistors, fabricated in the same batch The addition of the source resistor permits adjusting the current source output, as shown below With a source resistor in the circuit, as shown in Figure 944(a), KVL applied around the gate-source circuit yields vGS = iD RGS Applying the drain current equation for the saturation region, we have: iD = IDSS (vGS + VP )2 = IDSS 2 VP vGS +1 VP
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