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Figure 1011 DC bias circuit for the common-emitter ampli er
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In these equations, the quiescent emitter current, IEQ , has been expressed in terms of the collector current, ICQ , according to the relation IEQ = +1 ICQ (1018)
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The next two examples illustrate a number of practical issues in the choice of DC bias point, and in the determination of other important features of the common-emitter transistor ampli er
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EXAMPLE 103 Analysis of Common-Emitter Ampli er Operating Point
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Problem
Determine which of the two ampli ers designs, design A and design B, offers the better choice of operating point for the common-emitter ampli er of Figure 1012, and explain why one is superior to the other
RC +
Solution
Known Quantities: Ampli er supply voltages; base, collector, and emitter resistances;
transistor parameters
Find: Quiescent values of IB , IC , and VCE for each design Schematics, Diagrams, Circuits, and Given Data: V = 07 V; = 100; VCC = 15 V
+ ~
Vin R2 R3
Vout
Design A: R1 = 68 k ; R2 = 117 k ; RC = 200 ; RE = 200 Design B: R1 = 237 k ; R2 = 173 k ; RC = 200 ; RE = 200
Figure 1012 Common-emitter ampli er for Example 103
Assumptions: Use the linear small-signal h-parameter model of the BJT
15 V
Analysis:
1 Design A The DC equivalent supply seen by the transistor is shown in Figure 1013 We can compute the equivalent base supply and resistance as follows (also see Example 96): VBB = R1 117 VCC = 15 = 22 V R1 + R2 117 + 68 68 117 10 k 68 + 117
68 k B 117 k
RB B
and the equivalent base resistance from equation 97: RB = R1 ||R2 =
Figure 1013 Equivalent base supply circuit of design A
10
Transistor Ampli ers and Switches
RB V IB VBB IE RE
Next, we consider the equivalent base-emitter circuit, shown in Figure 1014 Applying KVL we compute the base and collector currents as follows: VBB = IB RB + V + IE RE = IB RB + V + ( + 1)IB RE IB = VBB V 22 07 = 50 A = RB + ( + 1)RE 10,000 + 101 200
IC = IB = 5 mA
Figure 1014 Equivalent base-emitter circuit of design A
Next, we turn to the equivalent collector-emitter circuit (see Figure 1015), and apply KVL to determine the collector-emitter voltage: VCC = IC RC + VCE + IE RE = IC RC + VCE + ( + 1) I C RE 101 200 100
RC + VCE _ RE
VCE = VCC IC RC + = 13 V
( + 1) RE
= 15 5 10 3 200 +
Thus, the Q point for the ampli er of design A is:
IBO = 50 A
Figure 1015 Collector-emitter circuit of design A
ICO = 5 mA
VCEO = 13 V
2 Design B We repeat the calculations of part 1 for the ampli er of design B: VBB = R1 173 15 = 633 V VCC = R1 + R 2 237 + 173 173 237 10 k 173 + 237
RB = R1 ||R2 = IB =
VBB V 633 07 = 186 A = RB + ( + 1)RE 10,000 + 101 200 ( + 1) RE 101 200 = 75 V 100
IC = IB = 186 mA VCE = VCC IC RC +
= 15 186 10 3 200 +
Thus, the Q point for the ampli er of design B is:
IBO = 186 A
ICO = 186 mA
VCEO = 75 V
To compare the two designs, we plot the load line in the IC VCE plane, and observe that the maximum collector current swing that can be achieved by design B is far greater than that permitted by design A (Figure 1016) The reason is quite simply that the Q point of design B is much closer to the center of the active region of the transistor, while the Q point of design A will cause the transistor to move into the cutoff region if the collector current swing is to be more than a couple of milliamperes
Part II
IC (mA)
375 mA
Electronics
40 30
Load line
Maximum collector current swing (B)
Design B Maximum collector Design current swing (A) A
186 mA 20
5 mA
0 VCE sat
VCE (V)
Figure 1016 Operating points for designs A and B
Comments: A simple rule that can be gleaned from this example is that, for linear ampli er designs, it is desirable to place the Q point near the center of the collector characteristic active region Focus on Computer-Aided Tools: This example is available as an Electronics WorkbenchTM simulation in the accompanying CD-ROM Both circuits are simulated, and you can verify that design A leads to cutoff distortion by applying an AC input signal larger than a few millivolts to the ampli er of design A Another virtual experiment that you can run is to increase the amplitude of the input signal for the ampli er of design B and determine the maximum sinusoidal input voltage amplitude that can be ampli ed without distortion What causes distortion rst: cutoff or saturation
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