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logic values are actually quite exible, with vHIGH as low as 24 V and vLOW as high as 04 V
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Transistor Ampli ers and Switches
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Analysis: The inputs to the TTL gate, v1 and v2 , are applied to the emitter of transistor
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Q1 The transistor is designed so as to have two emitter circuits in parallel Q1 is modeled by the offset diode model, as shown in Figure 1049 We shall now consider each of the four cases 1 v1 = v2 = 0 V With the emitters of Q1 connected to ground and the base of Q1 at 5 V, the BE junction will clearly be forward biased and Q1 is on This result means that the base current of Q2 (equal to the collector current of Q1 ) is negative, and therefore Q2 must be off If Q2 is off, its emitter current must be zero, and therefore no base current can ow into Q3 , which is in turn also off With Q3 off, no current ows through R3 , and therefore vout = 5 vR3 = 5 V
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2 v1 = 5 V; v2 = 0 V Now, with reference to Figure 1049, we see that diode D1 is still forward-biased, but D2 is now reverse-biased because of the 5-V potential at v2 Since one of the two emitter branches is capable of conducting, base current will ow and Q1 will be on The remainder of the analysis is the same as in case (1), and Q2 and Q3 will both be off, leading to vout = 5 V 3 v1 = 0 V; v2 = 5 V By symmetry with case (2), we conclude that, again, one emitter branch is conducting, and therefore Q1 will be on, Q2 and Q3 will both be off, and vout = 5 V 4 v1 = 5 V; v2 = 5 V When both v1 and v2 are at 5 V, diodes D1 and D2 are both strongly reverse-biased, and therefore no emitter current can ow Thus, Q1 must be off Note, however, that while D1 and D2 are reverse-biased, D3 is forward-biased, and therefore a current will ow into the base of Q2 ; thus, Q2 is on and since the emitter of Q2 is connected to the base of Q3 , Q3 will also see a positive base current and will be on To determine the output voltage, we assume that Q3 is operating in saturation Then, applying KVL to the collector circuit we have: VCC = IC3 R3 + VCE3 or IC3 = and vout = VCC IC R3 = 5 22 10 3 22 10 3 = 5 484 = 016 V These results are summarized in the table below The output values are consistent with TTL logic; the output voltage for case (4) is suf ciently close to zero to be considered zero for logic purposes VCC VCE3 VCC VCE sat 5 02 = = = 22 mA RC RC 2,200
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v1 0V 0V 5V 5V
v2 0V 5V 0V 5V
State of Q2 Off Off Off On
State of Q3 Off Off Off On
vout 5V 5V 5V 016 V
Comments: While exact analysis of TTL logic gate circuits could be tedious and
involved, the method demonstrated in this example to determine whether transistors are on or off leads to very simple analysis Since in logic devices one is interested primarily
Part II
Electronics
in logic levels and not in exact values, this approximate analysis method is very appropriate
Focus on Computer-Aided Solutions: An Electronics WorkbenchTM simulation of the
TTL NAND gate may be found in the accompanying CD-ROM You may wish to validate the saturation assumption for transistors Q2 and Q3 by measuring VCE2 and VCE3 in the simulation
The analysis method employed in Example 1011 can be used to analyze any TTL gate With a little practice, the calculations of this example will become familiar The Check Your Understanding exercises and homework problems will reinforce the concepts developed in this section
MOSFET Logic Gates
Having discussed the BJT as a switching element, we might suspect that FETs may similarly serve as logic gates In fact, in some respects, FETs are better suited to be employed as logic gates than BJTs The n-channel enhancement MOSFET, discussed in 9, serves as an excellent illustration: because of its physical construction, it is normally off (that is, it is off until a suf cient gate voltage is provided), and therefore it does not require much current from the input signal source Further, MOS devices offer the additional advantage of easy fabrication into integrated circuit form, making production economical in large volume On the other hand, MOS devices cannot provide as much current as BJTs, and their switching speeds are not quite as fast although these last statements may not hold true for long, because great improvements are taking place in MOS technology Overall, it is certainly true that in recent years it has become increasingly common to design logic circuits based on MOS technology In particular, a successful family of logic gates called CMOS (for complementary metal-oxide-semiconductor) takes advantage of both p- and n-channel enhancement-mode MOSFETs to exploit the best features of both types of transistors CMOS logic gates (and many other types of digital circuits constructed by using the same technology) consume very little supply power, and have become the mainstay in pocket calculators, wristwatches, portable computers, and many other consumer electronics products Without delving into the details of CMOS technology (a brief introduction is provided in 9), we shall brie y illustrate the properties of MOSFET logic gates and of CMOS gates in the remainder of this section Figure 1050 depicts a MOSFET switch with its drain i-v characteristic Note the general similarity with the switching characteristic of the BJT shown in the previous section When the input voltage, vin , is zero, the MOSFET conducts virtually no current, and the output voltage, vout , is equal to VDD When vin is equal to 5 V, the MOSFET Q point moves from point A to point B along the load line, with vDS = 05 V Thus, the circuit acts as an inverter Much as in the case of the BJT, the inverter forms the basis of all MOS logic gates An elementary CMOS inverter is shown in Figure 1051 Note rst the simplicity of this con guration, which simply employs two enhancement-mode MOSFETs: p-channel at the top, denoted by the symbol Qp , and n-channel at the bottom, denoted by Qn Recall from 9 that when vin is low, transistor Qn
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