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VDD RD vout vin
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MOSFET inverter VGS = 5 V B 1 RD 4V 3V 2V 1V 0 5 vDS (V) VDD = 5 V Switching characteristic 1 2 3 4 A
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iD VDD RD
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Figure 1050 MOSFET switching characteristic
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Transistor Ampli ers and Switches
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VDD vGS + vin Qn + vGS Qn CMOS Inverter Simplified CMOS Inverter model Qp vout
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vin = Low VDD Qp vout
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vin = High VDD Qp vout Qn
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Figure 1051 CMOS Inverter and circuit model
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is off However, transistor Qp sees a gate-to-source voltage vGS = vin VDD = VDD ; in a p-channel device, this condition is the counterpart of having vGS = VDD for an n-channel MOSFET Thus, when Qn is off, Qp is on and acts very much as a small resistance In summary, when vin is low, the output is vout VDD When vin is high, the situation is reversed: Qn is now on and acts nearly as a short circuit, while Qp is open (since vGS = 0 for Qp ) Thus, vout 0 The complementary MOS operation is depicted in Figure 1051 in simpli ed form by showing each transistor as either a short or an open circuit, depending on its state This simpli ed analysis is suf cient for the purpose of a qualitative analysis The following examples illustrate methods for analyzing MOS switches and gates
EXAMPLE 1012 MOSFET Switch
Problem
Determine the operating points of the MOSFET switch of Figure 1052 when the signal source outputs zero volts and 25 volts, respectively
+ _ vsignal (t)
Solution
Known Quantities: Drain resistor; VDD ; signal source output voltage as a function of
time
Find: Q point for each value of the signal source output voltage Figure 1052 Schematics, Diagrams, Circuits, and Given Data: RD = 125 vsignal (t) = 0 V for t < 0; vsignal (t) = 25 V for t = 0
; VDD = 10 V;
Assumptions: Use the drain characteristic curves for the MOSFET (Figure 1053) Analysis: We rst draw the load line using the drain circuit equation:
VDD = RD ID + VDS
10 = 125ID + VDS
recognizing a VDS axis intercept at 10 V and an ID axis intercept at 10/125 = 80 mA
Part II
Electronics
iD mA 80
vGS = 26 V 24 V 22 V 20 V 18 V 16 V
2 25
4 VDD
10 vDS (V)
Figure 1053 Drain curves for MOSFET of Figure 1052
1 t < 0 s When the signal source output is zero, the gate voltage is zero and the MOSFET is in the cutoff region The Q point is: VGSQ = 0 V IDQ = 0 mA VDSQ = 10 V
2 t 0 s When the signal source output is 25 V, the gate voltage is 25 V and the MOSFET is in the saturation region The Q point is: VGSQ = 0 V IDQ = 60 mA VDSQ = 25 V
This result satis es the drain equation, since RD ID = 006 125 = 75 V
Comments: The simple MOSFET con guration shown can quite effectively serve as a switch, conducting 60 mA when the gate voltage is switched to 25 V
EXAMPLE 1013 CMOS Gate
Problem
Determine the logic function implemented by the CMOS gate of Figure 1054 Use the table below to summarize the behavior of the circuit
v1 0V 0V 5V 5V
v2 0V 5V 0V 5V
State of M1
State of M2
State of M3
State of M4
vout
Solution
Find: vout for each of the four combinations of v1 and v2
10
Transistor Ampli ers and Switches
M1 v1 vout M2 v2 VDD M3 M4 The transistors in this circuit show the substrate for each transistor connected to its respective gate In a true CMOS IC, the substrates for the p-channel transistors are connected to 5 V and the substrates of the n-channel transistors are connected to ground
v2 M2 vout
Schematics, Diagrams, Circuits, and Given Data: VT = 17 V; VDD = 5 V Assumptions: Treat the MOSFETs as open circuits when off and as linear resistors
M3 v1
when on
Analysis:
5V M1 M2 vout M3 M4
1 v1 = v2 = 0 V With both input voltages equal to zero, neither M3 nor M4 can conduct, since the gate voltage is less than the threshold voltage for both transistors M1 and M2 will similarly be off, and no current will ow through the drain-source circuits of M1 and M2 Thus, vout = VDD = 5 V This condition is depicted in Figure 1055 2 v1 = 5 V; v2 = 0 V Now M2 and M4 are off because of the zero gate voltage, while M1 and M3 are on Figure 1056 depicts this condition 3 v1 = 0 V; v2 = 5 V By symmetry with case (2), we conclude that, again, one emitter branch is conducting, and therefore Q1 will be on, Q2 and Q3 will both be off, and vout = 5 V See Figure 1057 4 v1 = 5 V; v2 = 5 V When both v1 and v2 are at 5 V, diodes D1 and D2 are both strongly reverse-biased, and therefore no emitter current can ow Thus, Q1 must be off Note, however, that while D1 and D2 are reverse-biased, D3 is forward-biased, and therefore a current will ow into the base of Q2 ; thus, Q2 is on, and, since the emitter of Q2 is connected to the base of Q3 , Q3 will also see a positive base current
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