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CD 00 00 01 11 10 1 0 0 1 01 1 1 1 1 11 0 0 1 1 10 1 0 0 0
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A B y C D
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Figure 1337 Karnaugh map for Example 139
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Figure 1338 Logic circuit realization of Karnaugh map of Figure 1337
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The implementation of the above function with logic gates is shown in Figure 1338
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Comments: The Karnaugh map covering of Figure 1337 is a sum-of-products
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expression because we covered the map using the ones
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EXAMPLE 1310 Deriving a Sum-of-Products Expression from a Logic Circuit
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Problem
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Derive the truth table and minimum sum-of-products expression for the circuit of Figure 1339
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Part II
Electronics
Solution
Known Quantities: Logic circuit representing f (x, y, z) Find: Expression for f and corresponding truth table Analysis: To determine the truth table, we write the expression corresponding to the
logic circuit of Figure 1339: f =x y+y z The truth table corresponding to this expression and the corresponding Karnaugh map with sum-of-products covering are shown in Figure 1340
x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 f 1 1 0 1 0 0 0 1 x
yz 00 0 1 1 0 01 1 0 11 1 1 10 0 0
K map
Figure 1340 Comments: If we used zeros in covering the Karnaugh map for this example, the resulting
expression would be a product-of-sums You may verify that, in the case of this example, the complexity of the circuit would be unchanged Note also that there exists a third subcube (x = 0, yz = 01, 11) that is not used because it does not help minimize the solution
EXAMPLE 1311 Realizing a Product-of-Sums Using Only NAND Gates
Problem
Realize the following function in sum-of-products form, using only two-input NAND gates f = (x + y) (y + z)
Solution
Known quantities: f (x, y, z) Find: Logic circuit for f using only NAND gates Analysis: The rst step is to convert the expression for f into an expression that can be
easily implemented with NAND gates We observe that direct application of De Morgan s theorem yields: x+y =x y y+z=z y Thus, we can write the function as follows: f = (x y) z y and implement it with ve NAND gates, as shown in Figure 1341
13
Digital Logic Circuits
Comments: Note that we used two NAND gates as inverters one to obtain y, the other
to invert the output of the fourth NAND gate, equal to (x y) z y
EXAMPLE 1312 Simplifying Expressions by Using Karnaugh Maps
Problem
Simplify the following expression by using a Karnaugh map f =x y+x z+y z
Solution
yz 00 0 1 0 0 01 1 0 11 1 1 xz 10 0 1
Known Quantities: f (x, y, z) Find: Minimal expression for f Analysis: We cover a three-term Karnaugh map to re ect the expression give above The result is shown in Figure 1342 It is clear that the Karnaugh map can be covered by using just two terms (subcubes): f = x y + x z Thus, the term y z is redundant Comments: The Karnaugh map covering clearly shows that the term y z corresponds to covering a third two-cell subcube vertically intersecting the two horizontal two-cell subcubes already shown Clearly, the third subcube is redundant
K map xy
EXAMPLE 1313 Simplifying a Logic Circuit by Using the Karnaugh Map
Problem
y f z
Derive the Karnaugh map corresponding to the circuit of Figure 1343 and use the resulting map to simplify the expression
Solution
Known Quantities: Logic circuit Figure 1343 Find: Simpli ed logic circuit
Part II
Electronics
Analysis: We rst determine the expression f (x, y, z) from the logic circuit:
f = (x z) + (x z) + (y z) This expression leads to the Karnaugh map shown in Figure 1344 Inspection of the Karnaugh map reveals that the map could have been covered more ef ciently by using four-cell subcubes The improved map covering, corresponding to the simpler function f = x + z, and the resulting logic circuit are shown in Figure 1345
yz 00 0 1 1 1 01 0 1 11 0 1 10 1 1 x x f z yz 00 0 1 1 1 01 0 1 11 0 1 10 1 1
f=x+z
f = yz + xz + yz
K map
Figure 1345 Comments: In general, one wishes to cover the largest possible subcubes in a Karnaugh
map
Product-of-Sums Realizations Thus far, we have exclusively worked with sum-of-products expressions, that is, logic functions of the form A B + C D We know, however, that De Morgan s laws state that there is an equivalent form that appears as a product of sums, for example, (W + Y ) (Y + Z) The two forms are completely equivalent, logically, but one of the two forms may lead to a realization involving a smaller number of gates When using Karnaugh maps, we may obtain the product-of-sums form very simply by following these rules:
F O C U S O N M E T H O D O L O G Y
Product-of-Sums Realizations 1 Solve for the 0s exactly as for the 1s in sum-of-products expressions 2 Complement the resulting expression
The same principles stated earlier apply in covering the map with subcubes and determining the minimal expression The following examples illustrate how one form may result in a more ef cient solution than the other
13
Digital Logic Circuits
EXAMPLE 1314 Comparison of Sum-of-Products and Product-of-Sums Designs
Problem
x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 f 0 1 1 1 1 1 0 0
Realize the function f described by the accompanying truth table using both 0 and 1 coverings in the Karnaugh map
Solution
Known Quantities: Truth table for logic function Find: Realization in both sum-of-products and product-of-sums forms Analysis:
Product-of-sums expression Product-of-sums expressions use zeros to determine the logical expression from a Karnaugh map Figure 1346 depicts the Karnaugh map covering with zeros, leading to the expression f = (x + y + z) (x + y)
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