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1317 Simplify the following expression, using a Karnaugh map:
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1318 The function y of Example 139 can be obtained with fewer gates if we use gates with three or four inputs Find the minimum number of gates needed to obtain this function 1319 Verify that the product-of-sums expression for Example 1314 can be realized with fewer gates 1320 Would a sum-of-products realization for Example 1315 require fewer gates 1321 Prove that the circuit of Figure 1351 can also be obtained from the sum of
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1322 In Example 1316, assign a value of 0 to the don t care terms and derive the corresponding minimal expression Is the new function simpler than the one obtained in Example 1316 1323 In Example 1317, assign a value of 0 to the don t care terms and derive the corresponding minimal expression Is the new function simpler than the one obtained in Example 1317 1324 In Example 1317, assign a value of 1 to all don t care terms and derive the corresponding minimal expression Is the new function simpler than the one obtained in Example 1317
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1325 In Example 1318, assign a value of 0 to all don t care terms and derive the corresponding minimal expression Is the new function simpler than the one obtained in Example 1318 1326 In Example 1318, assign a value of 1 to all don t care terms and derive the corresponding minimal expression Is the new function simpler than the one obtained in Example 1318
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The basic logic gates described in the previous section are used to implement more advanced functions and are often combined to form logic modules, which, thanks to modern technology, are available in compact integrated circuit (IC) packages In this section and the next, we discuss a few of the more common combinational logic modules, illustrating how these can be used to implement advanced logic functions Multiplexers Multiplexers, or data selectors, are combinational logic circuits that permit the selection of one of many inputs A typical multiplexer (MUX) has 2n data lines, n address (or data select) lines, and one output In addition, other control inputs (eg, enables) may exist Standard, commercially available MUXs allow for n up to 4; however, two or more MUXs can be combined if a greater range is needed The MUX allows for one of 2n inputs to be selected as the data output; the selection of which input is to appear at the output is made by way of the address lines Figure 1355 depicts the block diagram of a four-input MUX The input data lines are labeled D0 , D1 , D2 , and D3 ; the data select, or address, lines are labeled I0 and I1 ; and the output is available in both complemented and uncomplemented form, and is thus labeled F , or F Finally, an enable input, labeled E, is also provided, as a means of enabling or disabling the MUX: if E = 1, the MUX is disabled; if E = 0, it is enabled The negative logic (MUX off when E = 1 and on when E = 0) is represented by the small bubble at the enable input, which represents a complement operation (just as at the output of NAND and NOR gates) The enable input is useful whenever one is interested in a cascade of MUXs; this would be of interest if we needed to select a line from a large number, say 28 = 256 Then two 4-input MUXs could be used to provide the data selection of 1 of 8 The material described in the previous sections is quite adequate to describe the internal workings of a multiplexer Figure 1356 shows the internal construction of a 4-to-1 MUX using exclusively NAND gates (inverters are also used, but the reader will recall that a NAND gate can act as an inverter if properly connected) In the design of digital systems (for example, microcomputers), a single line is often required to carry two or more different digital signals However, only one signal at a time can be placed on the line A MUX will allow us to select, at different instants, the signal we wish to place on this single line This property is shown here for a 4-to-1 MUX Figure 1357 depicts the functional diagram of a 4-to-1 MUX, showing four data lines, D0 through D3 , and two select lines, I0 and I1 The data selector function of a MUX is best understood in terms of Table 1313 In this truth table, the x s represent don t care entries As can be seen from the truth table, the output selects one of the data lines depending on the values of
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