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S Inputs R
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Q Outputs Q
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It is customary to depict ip- ops by their block diagram and a name such as Q or X representing the output variable Figure 141 represents the so-called RS ip- op, which has two inputs, denoted by S and R, and two outputs, Q and Q The value at Q is called the state of the ip- op If Q = 1, we refer to the device as being in the 1 state Thus, we need de ne only one of the two outputs of the ip- op The two inputs, R and S, are used to change the state of the ip- op, according to the following rules: 1 When R = S = 0, the ip- op remains in its present state (whether 1 or 0) 2 When S = 1 and R = 0, the ip- op is set to the 1 state (thus, the letter S, for set) 3 When S = 0 and R = 1, the ip- op is reset to the 0 state (thus, the letter R, for reset) 4 It is not permitted for both S and R to be equal to 1 (This would correspond to requiring the ip- op to set and reset at the same time)
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S 0 0 1 1
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R 0 1 0 0 Reset Set
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Q Present state
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Figure 141 RS ip- op symbol and truth table
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Electronics
The rules just described are easily remembered by noting that 1s on the S and R inputs correspond to the set and reset commands, respectively A convenient means of describing the series of transitions that occur as the signals sent to the ip- op inputs change is the timing diagram A timing diagram is a graph of the inputs and outputs of the RS ip- op (or any other logic device) depicting the transitions that occur over time In effect, one could also represent these transitions in tabular form; however, the timing diagram provides a convenient visual representation of the evolution of the state of the ip- op Figure 142 depicts a table of transitions for an RS ip- op Q, as well as the corresponding timing diagram
S 1 0 0 0 0 0 0 0 1 0
R 0 0 0 1 0 0 1 0 0 0
Q 1 1 1 0 0 0 0 0 1 1
Time 1 S 0 1 R 0 1 Q 0 Flip-flop Flip-flop Flip-flop Flip-flop is reset is reset is set is set (but Q = 0) already
Figure 142 Timing diagram for the RS ip- op
It is important to note that the RS ip- op is level-sensitive This means that the set and reset operations are completed only after the R and S inputs have reached the appropriate levels Thus, in Figure 142 we show the transitions in the Q output as occurring with a small delay relative to the transitions in the R and S inputs It is instructive to illustrate how an RS ip- op can be constructed using simple logic gates For example, Figure 143 depicts a realization of such a circuit consisting of four gates: two inverters and two NAND gates (actually, the same result could be achieved with four NAND gates) Consider the case in which the circuit is in the initial state Q = 0 (and therefore Q = 1) If the input S = 1 is applied, the top NOT gate will see inputs Q = 1 and S = 0, so that Q = (S Q) = (0 1) = 1 that is, the ip- op is set Note that when Q is set to 1, Q becomes 0 This, however, does not affect the state of the Q output, since replacing Q with 0 in the expression Q = (S Q) does not change the result: Q = (0 0) = 1 Thus, the cross-coupled feedback from outputs Q and Q to the input of the NAND gates is such that the set condition sustains itself It is straightforward to show (by symmetry) that a 1 input on the R line causes the device to reset (ie, causes Q = 0) and that this condition is also self-sustaining
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