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Figure 145 Data latch and associated timing diagram
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Q1 D S1 R1 E1 CLK Functional diagram Q1 Q1 S2 R2 E2 Device symbol CLK Q2 Q2 Q Q CLK Q D Q Q = Q2
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Figure 146 D ip- op functional diagram, symbol, and timing waveforms
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device symbol The particular device described here is said to be positive edge triggered, or leading edge triggered, since the nal output of the ip- op is set on a positive-going clock transition On the basis of the rules stated in this section, the state of the D ip- op can be described by means of the following truth table:
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D 0 1
CLK
Q 0 1
where the symbol indicates the occurrence of a positive transition
Part II
Electronics
JK Flip-Flop
Another very common type of ip- op is the JK ip- op, shown in Figure 147 The JK ip- op operates according to the following rules:
When J and K are both low, no change occurs in the state of the ip- op When J = 0 and K = 1, the ip- op is reset to 0 When J = 1 and K = 0, the ip- op is set to 1 When both J and K are high, the ip- op will toggle between states at every negative transition of the clock input, denoted from here on by the symbol
J CLK K
Master Q1 S1 E1 R1 Q1
Slave S2 E2 R2 Q2 Q2 Q Q J CLK K Q Q
Device symbol
Functional diagram
Figure 147 JK ip- op functional diagram and device symbol
Note that, functionally, the operation of the JK ip- op can also be explained in terms of two RS ip- ops When the clock waveform goes high, the master ip- op is enabled; the slave receives the state of the master upon a negative clock transition The bubble at the clock input signi es that the device is negative or trailing edge triggered This behavior is similar to that of an RS ip- op, except for the J = 1, K = 1 condition, which corresponds to a toggle mode rather than to a disallowed combination of inputs Figure 148 depicts the truth table for the JK ip- op It is important to note that when both inputs are 0 the ip- op remains in its previous state at the occurrence of a clock transition; when either input is high and the other is low, the JK ip- op behaves like the RS ip- op, whereas if both inputs are high, the output toggles between states every time the clock waveform undergoes a negative transition Data sheets for various types of ip- ops may be found in the accompanying CD-ROM
J CLK K
JK flip-flop Jn 0 0 1 1 Kn 0 1 0 1 Qn 0 (reset) 1 (set) Qn (toggle) Qn+1
Figure 148 Truth table for the JK ip- op
EXAMPLE 142 The T Flip-Flop
Problem
Determine the truth table and timing diagram of the T ip- op of Figure 149 Note that the T ip- op is a JK ip- op with its inputs tied together
14
Digital Systems
CLK t Input Clock T CLK Q T flip-flop Q Waveforms for (toggle mode) T flip-flop (T = 1) t Q Q t
Figure 149 T ip- op symbol and timing waveforms
Solution
Known Quantities: JK ip- op rules of operation (Figure 148) Find: Truth table and timing diagram for T ip- op Analysis: We recognize that the T ip- op is a JK ip- op with its inputs tied together Thus, the ip- op will need only a two-element truth table to describe its operation, corresponding to the top and bottom entries in the JK ip- op truth table of Figure 148 The truth table is shown below A timing diagram is also included in Figure 149
T 0 1
CLK
Qk+1 Qk Qk
Comments: The T ip- op takes its name from the fact that it toggles between the high and low state Note that the toggling frequency is one half that of the clock Thus the T ip- op also acts as a divide-by-2 counter Counters are explored in more detail in the next subsection
EXAMPLE 143 JK Flip-Flop Timing Diagram
Problem
Determine the output of a JK ip- op for the series of inputs given in the table below The initial state of the ip- op is Q0 = 1 J K 0 0 1 1 0 1 1 0 0 0 0 1 1 1
Solution
Known Quantities: JK ip- op truth table (Figure 148) Find: Output of RS ip- op, Q, as a function of the input transitions
Part II
Electronics
Analysis: We complete the timing diagram for the JK ip- op following the rules of Figure 148; the result is summarized below
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