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A sketch of the waveforms, shown below, can also be generated to visualize the transitions Each vertical line corresponds to a clock transition
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Comments: How would the timing diagram change if the initial state of the ip- op were Q0 = 1
Digital Counters One of the more immediate applications of ip- ops is in the design of counters A counter is a sequential logic device that can take one of N possible states, stepping through these states in a sequential fashion When the counter has reached its last state, it resets to zero and is ready to start counting again For example, a threebit binary up counter would have 23 = 8 possible states, and might appear as shown in the functional block of Figure 1410 The input clock waveform causes the counter to step through the eight states, making one transition for each clock pulse We shall shortly see that a string of JK ip- ops can accomplish this task exactly The device shown in Figure 1410 also displays a reset input, which forces the counter output to equal 0: b2 b1 b0 = 000 Although binary counters are very useful in many applications, one is often interested in a decade counter, that is, a counter that counts from 0 to 9 and then resets A four-bit binary counter can easily be con gured in principle to provide this function by means of simple logic that resets the counter when it has reached the count 10012 = 910 As shown in Figure 1411, if we connect bits b3 and b1 to a four-input AND gate, along with b2 and b0 , the output of the AND gate can be used to reset the counter after a count of 10 Additional logic can provide a carry bit whenever a reset condition is reached, which could be passed along to another decade counter, enabling counts up to 99 Decade counters can be cascaded so as to represent decimal digits in succession Although the decade counter of Figure 1411 is attractive because of its simplicity, this con guration would never be used in practice, because of the
14
Digital Systems
Reset
Input pulses 0
State b2 b1 b0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Clock input
3-bit binary counter
1 2 3 4 5 6 7
b2 b1 b0 Functional representation of binary counter Clock
Timing table
t b0
t b1
t b2
Timing diagram
Figure 1410 Binary up counter functional representation, state table, and timing waveforms
Input pulses 0 1 2 3 4 5 6 7 8 9 10
b 3 b2 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0
b1 0 0 1 1 0 0 1 1 0 0 1
b0 0 1 0 1 0 1 0 1 0 1 0 Reset b3 b2 Clock 4-bit binary counter b1 b0 Reset
Figure 1411 Decade counter
presence of propagation delays These delays are caused by the nite response time of the individual transistors in each logic device and cannot be guaranteed to be identical for each gate and ip- op Thus, if the reset signal which is presumed to be applied at exactly the same time to each of the four JK ip- ops in the four-bit
Part II
Electronics
binary counter does not cause the JK ip- ops to reset at exactly the same time on account of different propagation delays, then the binary word appearing at the output of the counter will change from 1001 to some other number, and the output of the four-input NAND gate will no longer be high In such a condition, the ip- ops that have not already reset will then not be able to reset, and the counting sequence will be irreparably compromised What can be done to obviate this problem The answer is to use a systematic approach to the design of sequential circuits making use of state transition diagrams This topic will be discussed in the next section A simple implementation of the binary counter we have described in terms of its functional behavior is shown in Figure 1412 The gure depicts a three-bit binary ripple counter, which is obtained from a cascade of three JK ip- ops The transition table shown in the gure illustrates how the Q output of each stage becomes the clock input to the next stage, while each ip- op is held in the toggle mode The output transitions assume that the clock, CLK, is a simple square wave (all JKs are negative edge triggered)
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