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Q3 0 0 0 0 1 1 1
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J Clock input CLK K
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Figure 1412 Ripple counter
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This 3-bit ripple counter can easily be con gured as a divide-by-8 mechanism, simply by adding an AND gate To divide the input clock rate by 8, one output pulse should be generated for every eight clock pulses If one were to output a pulse every time a binary 111 combination occurs, a simple AND gate would suf ce to generate the required condition This solution is shown in Figure 1413 Note that the square wave is also included as an input to the AND gate; this ensures that the output is only as wide as the input signal This application of ripple counters is further illustrated in the following example
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J CLK K
J CLK K
J CLK K
Figure 1413 Divide-by-8 circuit
14
Digital Systems
EXAMPLE 144 Divider Circuit
Problem
Draw the timing diagram for the clock input, Q0 and Q1 , for the binary ripple counter of Figure 1414
Q0 VCC
J CLK K
J CLK K
Solution
Known Quantities: JK ip- op truth table (Figure 148) Find: Output of each ip- op, Q, as a function of the input clock transitions Assumptions: Assume negative-edge triggered devices Analysis: Following the timing diagram of Figure 1412, we see that Q0 switches at half the frequency of the clock input, and that Q1 switches at half the frequency of Q0 Hence the timing diagram shown below
T CLK
Q0 Q1 2T 4T
A slightly more complex version of the binary counter is the so-called synchronous counter, in which the input clock drives all of the ip- ops simultaneously Figure 1415 depicts a three-bit synchronous counter In this gure, we have chosen to represent each ip- op as a T ip- op The clocks to all the ip- ops are incremented simultaneously The reader should verify that Q0 toggles to 1 rst and then Q1 toggles to 1, and that the AND gate ensures that Q2 will toggle only after Q0 and Q1 have both reached the 1 state (Q0 Q1 = 1)
Part II
Electronics
T CLK
CLK Q0 Clock input
CLK Q1
Figure 1415 Three-bit synchronous counter
Other common counters are the ring counter, illustrated in Example 145, and the up-down counter, which has an additional select input that determines whether the counter counts up or down Data sheets for various counters may be found in the accompanying CD-ROM
EXAMPLE 145 Ring Counter
Problem
Draw the timing diagram for the ring counter of Figure 1416
Init Q3 Q2 Q1 Q0
PR Q3
CLR Q2
CLR Q1
CLR Q0
CLK R Q3
CLK R Q2
CLK R Q1
CLK R Q0
Clock input
Figure 1416 Ring counter
Solution
Known Quantities: JK ip- op truth table (Figure 148) Find: Output of each ip- op, Q, as a function of the input clock transitions Assumptions: Assume that prior to applying the clock input the Init line sees a positive
transition (this initializes the counter by setting the state of the rst ip- op to 1 through a PR (preset) input, and all other states to zero through a CLR (clear) input)
Analysis: With the initial state of Q3 = 0, a clock transition will set Q3 = 1 The clock also causes the other three ip- ops to see a reset input of 1, since
14
Digital Systems
Q3 = Q2 = Q1 = Q0 = 0 at the time of the rst clock pulse Thus, Q2 , Q1 and Q0 remain in the zero state At the second clock pulse, since Q3 is now 1, the second ip- op will see a set input of one, and its output will become Q2 = 1 Q1 and Q0 remain in the zero state, and Q3 is reset to 0 The pattern continues, causing the 1-state to ripple from left to right and back again This rightward rotation gives the counter its name The transition table is shown below
CLK Q3 1 0 0 0 1 0 0 Q2 0 0 1 0 0 1 0 Q1 0 1 0 0 0 0 1 Q0 0 0 0 1 0 0 0
Comments: The shifting function implemented by the ring counter is used in the shift
registers discussed in the following subsection
Focus on Computer-Aided Solutions: A ring counter simulation generated by
Electronics WorkbenchTM may be found in the accompanying CD-ROM
FOCUS ON MEASUREMENTS
Digital Measurement of Angular Position and Velocity
Another type of angular position encoder, besides the angular encoder discussed in 13 in Focus on Measurements: Position Encoders, is the slotted encoder shown in Figure 1417 This encoder can be used in conjunction with a pair of counters and a high-frequency clock to determine the speed of rotation of the slotted wheel As shown in Figure 1418, a clock of known frequency is connected to a counter while another counter records the number of slot pulses detected by an optical slot detector as the wheel rotates Dividing the counter values, one could obtain the speed of the rotating wheel in radians per second For example, assume a clocking frequency of 12 kHz If both counters are started at zero and at some instant the timer counter reads 2,850 and the encoder counter reads 3,050, then the speed of the rotating encoder is found to be: 1,200 and 1,1213 slots per second 1 per slot 2 /360 rad/degree = 196 rad/s If this encoder is connected to a rotating shaft, it is possible to measure the angular position and velocity of the shaft Such shaft encoders are used in measuring the speed of rotation of electric motors, machine tools, engines, and other rotating machinery cycles 2,850 slots slots = 1,1213 second 3,050 cycles second
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