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The power supply uses battery (BATT) and ignition (IGN) to provide different supply lines used by the controller circuitry One example would be an independent, close-tolerance, tracking voltage reference, for all sensors that are being read by the ADC The supply will operate reliably down to a battery voltage of 4 5 volts The CNOP signal provides a simple means of allowing the controller to perform housekeeping tasks prior to shutdown after IGN goes low
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Care must be taken to avoid ground loops13 within the controller that could result in interference with signal levels Typical methods employed for this include separation of signal grounds, power grounds, and radio-frequency grounds All three grounds have their own dedicated circuit board layer
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Sequential logic circuits are digital logic circuits with memory capabilities; their operation is described by state transition tables and state diagrams Counters and registers are the two principal classes of sequential circuits Sequential circuits can be designed using a formal procedure analogous to the use of Karnaugh maps for combinational circuits Digital systems play a prominent role in modern engineering The microprocessor, in particular, has become an integral part of instrumentation and control systems The microprocessor is very exible in its application because it can be programmed to perform many different tasks Depending on the computing power required, 8-, 16-, and 32-bit microprocessors are used for automating measurement and control functions in a variety of industrial applications
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CYU 143 45 kHz CYU 144 2,048 CYU 145 32,768
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Section 182 for an introduction to stepper motors Section 181 for an introduction to brushless DC motors 13 See Section 152 for an introduction to grounding and noise issues in circuit design
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Part II
Electronics
HOMEWORK PROBLEMS
141 The input to the circuit of Figure P141 is a square
wave having a period of 2 s, maximum value of 5 V, and minimum value of 0 V Assume all ip- ops are initially in the RESET state a Explain what the circuit does b Sketch the timing diagram, including the input and all four outputs
+5 V A0 J K Input pulse train Output #1 Output #2 Output #3 Output #4 Q Q J K Q Q J K Q Q J K Q Q J Q CLK K Q J Q CLK K Q
ip- ops Assuming that you have all the logic gates available, make a D ip- op using a T ip- op and some logic gate(s) 146 Draw a timing diagram (four complete clock cycles) for A0 , A1 , and A2 for the circuit of Figure P146 Assume that all initial values are 0 Note that all ip- ops are negative edge triggered
A2 A1 J Q CLK K Q
Figure P146
Figure P141
147 Assume that the slotted encoder shown in
Figure P147 has a length of 1 meter and a total of 1,000 slots (ie, there is one slot per millimeter) If a counter is incremented by 1 each time a slot goes past a sensor, design a digital counting system that determines the speed of the moving encoder (in meters per second)
1 mm
142 A binary pulse counter can be constructed by
interconnecting T -type ip- ops in an appropriate manner Assume it is desired to construct a counter which can count up to 10010 a How many ip- ops would be required b Sketch the circuit needed to implement this counter
143 Explain what the circuit of Figure P143 does and
how it works Hint: This circuit is called a 2-bit synchronous binary up-down counter
Q X T Q T
Figure P147
+5 V System clock Output #1 Output #2
148 Find the output Q for the circuit of Figure P148
D 1 2 3 4 5 6 7 8 9 10 11 t D Q Q CLK 1 2 3 4 5 6 7 8 9 10 11 t CLK
Figure P143
144 Suppose a circuit is constructed from 3 D-type
ip- ops, with D1 = Q2 Q 0 D2 = Q 1 D 0 = Q2 a Draw the circuit diagram b Assume the circuit starts with all ip- ops SET Sketch a timing diagram which shows the outputs of all three ip- ops
Figure P148
149 Describe how the ripple counter works Why is it
so named What disadvantages can you think of for this counter
145 Suppose that you want to use a D ip- op for a
laboratory experiment However, you have only T
14
Digital Systems
1410 Write the truth table for an RS ip- op with
enable (E), preset (P), and clear (C) lines 1411 A JK ip- op is wired as shown in Figure P1411 with a given input signal Assuming that Q is at logic 0 initially and the trailing edge triggering is effective, sketch the output Q
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