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Tracking ADC
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Figure 1527 Tracking ADC
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Although not the most ef cient in all applications, the tracking ADC is an easy starting point to illustrate the operation of an ADC, in that it is based on the DAC presented in the previous section The tracking ADC, shown in Figure 1527, compares the analog input signal with the output of a DAC; the comparator output determines whether the DAC output is larger or smaller than the analog input to be converted to binary form If the DAC output is smaller, then the comparator output will cause an up-down counter (see 14) to count up, until it reaches a level close to the analog signal; if the DAC output is larger than the analog signal, then the counter is forced to count down Note that the rate at which the up-down counter is incremented is determined by the external clock, and that the binary counter output corresponds to the binary representation of the analog signal A feature of the tracking ADC is that it follows ( tracks ) the analog signal by changing one bit at a time
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Part II
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Integrating ADC
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The integrating ADC operates by charging and discharging a capacitor, according to the following principle: if one can ensure that the capacitor charges (discharges) linearly, then the time it will take for the capacitor to discharge is linearly related to the amplitude of the voltage that has charged the capacitor In practice, to limit the time it takes to perform a conversion, the capacitor is not required to charge fully Rather, a clock is used to allow the input (analog) voltage to charge the capacitor for a short period of time, determined by a xed number of clock pulses Then the capacitor is allowed to discharge through a known circuit, and the corresponding clock count is incremented until the capacitor is fully discharged The latter condition is veri ed by a comparator, as shown in Figure 1528 The clock count accumulated during the discharge time is proportional to the analog voltage
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C Clock va R Vref + + Digital output Integrator Comparator Reset
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+V +
Figure 1528 Integrating ADC
In the gure, the switch causes the counter to reset when it is connected to the reference voltage, Vref The reference voltage is used to provide a known, linear discharge characteristic through the capacitor (see the material on the opamp integrator in 12) When the comparator detects that the output of the integrator is equal to zero, it switches state and disables the NAND gate, thus stopping the count The binary counter output is now the digital counterpart of the voltage va Other common types of ADC are the so-called successive-approximation ADC and the ash ADC
Flash ADC
R + R + R + R + R + R + R Encoder Digital output
The ash ADC is fully parallel and is used for high-speed conversion A resistive divider network of 2n resistors divides the known voltage range into that many equal increments A network of 2n 1 comparators then compares the unknown voltage with that array of test voltages All comparators with inputs exceeding the unknown are on ; all others are off This comparator code can be converted to conventional binary by a digital priority encoder circuit For example, assume that the three-bit ash ADC of Figure 1529 is set up with Vref = 8 V An input of 62 V is provided If we number the comparators from the top of Figure 1529, the state of each of the seven comparators is as given in Table 154
Figure 1529 A three-bit ash ADC
15
Electronic Instrumentation and Measurements
Table 154 State of comparators in a 3-bit ash ADC Input on + line 7V 6V 5V 4V 3V 2V 1V Input on line 62 V 62 V 62 V 62 V 62 V 62 V 62 V
Comparator 1 2 3 4 5 6 7
Output H L L L L L L
EXAMPLE 159 Flash ADC
Problem
How many comparators are needed in a 4-bit ash ADC
Solution
Known Quantities: ADC resolution Find: Number of comparators required Analysis: The number of comparators needed is 2n 1 = 15 Comments: The ash ADC has the advantage of high speed because it can
simultaneously determine the value of each bit thanks to the parallel comparators However, because of the large number of comparators, ash ADCs tend to be expensive
In the preceding discussion, we explored a few different techniques for converting an analog voltage to its digital counterpart; these methods and any others require a certain amount of time to perform the A/D conversion This is the ADC conversion time, and is usually quoted as one of the main speci cations of an ADC device A natural question at this point would be: If the analog voltage changes during the analog-to-digital conversion and the conversion process itself takes a nite time, how fast can the analog input signal change while still allowing the ADC to provide a meaningful digital representation of the analog input To resolve the uncertainty generated by the nite ADC conversion time of any practical converter, it is necessary to use a sample-and-hold ampli er The objective of such an ampli er is to freeze the value of the analog waveform for a time suf cient for the ADC to complete its task A typical sample-and-hold ampli er is shown in Figure 1530 It operates as follows A MOSFET analog switch (see 10) is used to sample the analog waveform Recall that when a voltage pulse is provided to the sample input of the MOSFET switch (the gate), the MOSFET enters the ohmic region and in
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