Resistive Network Analysis in Software

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Resistive Network Analysis
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familiarity with the techniques illustrated in this chapter will greatly simplify the study of AC circuits in 4 The objective of the chapter is to develop a solid understanding of the following topics:
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Node voltage and mesh current analysis The principle of superposition Th venin and Norton equivalent circuits e Numerical and graphical (load-line) analysis of nonlinear circuit elements
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THE NODE VOLTAGE METHOD
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In the node voltage method, we assign the node voltages va and vb; the branch current flowing from a to b is then expressed in terms of these node voltages va vb i= R va R i vb
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Figure 31 Branch current formulation in nodal analysis
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2 introduced the essential elements of network analysis, paving the way for a systematic treatment of the analysis methods that will be introduced in this chapter You are by now familiar with the application of the three fundamental laws of network analysis: KCL, KVL, and Ohm s law; these will be employed to develop a variety of solution methods that can be applied to linear resistive circuits The material presented in the following sections presumes good understanding of 2 You can resolve many of the doubts and questions that may occasionally arise by reviewing the material presented in the preceding chapter Node voltage analysis is the most general method for the analysis of electrical circuits In this section, its application to linear resistive circuits will be illustrated The node voltage method is based on de ning the voltage at each node as an independent variable One of the nodes is selected as a reference node (usually but not necessarily ground), and each of the other node voltages is referenced to this node Once each node voltage is de ned, Ohm s law may be applied between any two adjacent nodes in order to determine the current owing in each branch In the node voltage method, each branch current is expressed in terms of one or more node voltages; thus, currents do not explicitly enter into the equations Figure 31 illustrates how one de nes branch currents in this method You may recall a similar description given in 2 Once each branch current is de ned in terms of the node voltages, Kirchhoff s current law is applied at each node: i=0 (31)
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By KCL: i1 i2 i3 = 0 In the node voltage method, we express KCL by va vb vb vc vb vd =0 R1 R2 R3
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R1 i1
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vb i2 R2
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Figure 32 Use of KCL in nodal analysis
Figure 32 illustrates this procedure The systematic application of this method to a circuit with n nodes would lead to writing n linear equations However, one of the node voltages is the reference voltage and is therefore already known, since it is usually assumed to be zero (recall that the choice of reference voltage is dictated mostly by convenience, as explained in 2) Thus, we can write n 1 independent linear equations in the n 1 independent variables (the node voltages) Nodal analysis provides the minimum number of equations required to solve the circuit, since any branch voltage or current may be determined from knowledge of nodal voltages At this stage, you might wish to review Example 212, to verify that, indeed, knowledge of the node voltages is suf cient to solve for any other current or voltage in the circuit The nodal analysis method may also be de ned as a sequence of steps, as outlined in the following box:
Part I
Circuits
F O C U S O N M E T H O D O L O G Y
Node Voltage Analysis Method 1 Select a reference node (usually ground) All other node voltages will be referenced to this node 2 De ne the remaining n 1 node voltages as the independent variables 3 Apply KCL at each of the n 1 nodes, expressing each current in terms of the adjacent node voltages 4 Solve the linear system of n 1 equations in n 1 unknowns
Following the procedure outlined in the box guarantees that the correct solution to a given circuit will be found, provided that the nodes are properly identi ed and KCL is applied consistently As an illustration of the method, consider the circuit shown in Figure 33 The circuit is shown in two different forms to illustrate equivalent graphical representations of the same circuit The bottom circuit leaves no question where the nodes are The direction of current ow is selected arbitrarily (assuming that iS is a positive current) Application of KCL at node a yields: iS i 1 i 2 = 0 whereas, at node b, i2 i 3 = 0 (33) (32)
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