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Placing Components on PCBs Upon successful completion of the logical and gross timing simulation process, the actual physical layout can begin. It begins by placing the components of the design on the surface of the PCB in patterns that group logical functions together. Once this is done, the groups of components are located on the PCB surfaces such that functions that interact are adjacent, components that generate heat are cooled properly, components that interface to the outside world are near connectors, and so on. This placement operation can be done manually by the designer using graphics-based tools or automatically by the PCB CAD system.
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Sequencing Nets to High-Speed Rules Most logic families have sufficiently fast rise and fall times and short enough propogation delays to be subject to high-speed problems such as coupling and reflections. To ensure that these high-speed effects do not result in malfunctions, it is necessary to arrange the connections between the loads, terminations, and drivers to control these high-speed phenomena. This arranging of nodes or points in a net is referred to as sequencing or scheduling. Once the components have been placed on the surface of the PCB, the spatial arrangement of all the nodes on each net is known. At this point, it is possible to determine how to connect the driver to the loads and terminators to form proper transmission lines, ensuring that improper stubs are not created and that the terminator is at the end of the net.
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Simulating Timing and Transmission Lines Effects Upon completion of component placement and sequencing the nodes in each net, it is possible to estimate the length and characteristics of each net. This is possible because the x-y location of each point in a net is known, the order of connections is known, and the fact that the actual wiring must be done in either the x or y direction is also known. This length information can be used to model the high-speed switching characteristics of each net and predict the presence of excessive noise and reflections as well as to estimate the length of time required for signal to travel the length of each line, all before actually routing or building the PCB. This simulation step makes it possible to detect potential malfunctioning signals prior to routing and take steps to fix the problem while the time invested in the design is still modest.
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Adjusting Sequencing and Placement If the simulations done in Sec. 14.2.10 reveal excessive time delays or reflection problems, the placement may need to be adjusted to move critical parts closer together or add terminations to nets with excessive reflections. By doing this simulation and adjustment, a design can be assured of meeting the right the first time goal so important to high-performance designs.
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Testing Routability of Placement At this point, enough analysis has taken place to know that the design will function correctly if routed. However, it may not route in the number of signal layers required by the cost goal. Most CAD systems have tools, such as rats-nest analyzers, that help the designer determine if the design will fit into the allowed signal layers. If it will not, the routability analyzer may give clues on how to revise the component placement to achieve a successful route. Once the placement has been adjusted, the timing and transmission line simulation steps must be repeated to ensure that the set of goals has been met.
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THE PCB DESIGN PROCESS
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Routing PCB This step involves fitting all the connections into the signal layers in the form of copper traces, following spacing and length rules. It usually involves a combination of hand routing special signals and automatically routing the rest.
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Checking Routed Results After all the connections have been routed into the signal layers, the actual shape and length of each wire is known, as is the layer(s) on which the wires have been routed and which nets are neighbors. This physical data can be loaded into the timing and transmission line analyzers to do a final check that all design goals have been met. Any violations that are detected can be repaired by hand rerouting as necessary. Once this set of checks has been completed and any adjustments made, the final routed result is checked against the schematic netlist to ensure that there are no discrepancies. A final check is performed on the Gerber data to ensure that the line width and spacing rules have been complied with and that there is no solder mask of silk screen on any pad, as well as that traces and other features that must be protected from solder are covered by solder mask.
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Generating Manufacturing Files This step involves generating the photoplotting files, pick-and-place files, bare and loaded board test files, drawings, and bills of material needed to do the actual manufacturing. Typical lists of these files are shown in Tables 14.1 and 14.2.
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Archiving Design Once all the manufacturing data has been created, the design database and all of the manufacturing data files are stored on a magnetic tape or other storage media for future use to incorporate changes and for backup in the event that the files and drawings created for manufacturing are lost or destroyed.
TABLE 14.1 A Typical Collection of Design Files Sent to a PCB Fabricator File name BBBBpCCC.arc* applist.p ly1 thru lyx.ger topmsk.ger botmsk.ger topslk.ger botslk.ger pc_356.out name0.rep name0.prf name1.rep XX.XX.fab File contents Arc file of Gerber files containing: List of photoplot apertures for artwork Gerber photoplot data for x PCB layers Gerber photoplot data for top solder mask Gerber photoplot data for bottom solder mask Gerber photoplot data for top silk screen Gerber photoplot data for bottom silk screen IPC 356 data for blank PCB netlist testing Drill allocation report for plated holes Excellon drill file for all plated holes Drill allocation report for all nonplated holes Fabrication drawing in HPGL format, sheet XX of XX
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