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a. First RISC processor (1986) (8" 16" 14 layer-TH)
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b. Same RISC processor as MCM-L (1991) (4" 4" 10 layer-TH/Bv seq. lam) c. Same RISC processor as HDI (1995) (2" 2" 2+2+2 HDI-microvia)
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FIGURE 2.3 Example of the same computer CPU board as it used alternative component, assembly, and PWB technologies. (a) Size and appearance of each generation. (b) Movement of total board density from traditional to HDI. (c) HDI.
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A 14-layer board through-hole with a surface area of 128 in2 in 1986 (Fig. 2.3[a]) to A 10-layer surface-mount technology board with a surface area of 16 in2 in 1991 (Fig. 2.3[b]) to A high-density interconnect board with sequential build-up microvias, buried and blind vias, and a surface area of 4 in2 in 1995 (Fig. 2.3[c])
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Region of Advanced Technologies A second valuable feature of the chart in Fig. 2.2 is the area identified as the region of advanced technologies. This is where calculations and data have shown that it is necessary to have an HDI structure. Therefore, this is the barrier, or wall of HDI: on one side it is most cost effective to use traditional PWB technologies; on the other side it becomes cost effective to use HDI technologies. Continuing beyond this point, HDI becomes necessary.
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HIERARCHY OF INTERCONNECTIONS
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To have the proper perspective on where PWBs fit into electronic systems, it will be helpful to describe briefly the packaging hierarchy of electronic systems. Some time ago, the Institute for Interconnecting and Packaging Electronic Circuits (IPC)2 proposed eight categories of
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ELECTRONIC PACKAGING AND HIGH-DENSITY INTERCONNECTIVITY
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system elements in ascending order of size and complexity, which will be used here to illustrate typical electronic packaging structures. These are as follows: Category A consists of fully processed active and passive devices. Bare or uncased chips and discrete capacitors, resistors, or their networks are typical examples of this category. Category B comprises all packaged devices (active and passive) in plastic packages, such as DIPs, TSOPs, QFPs, and BGAs, as well as those in ceramic packages, such as PGAs, and connectors, sockets, and switches. All are ready to be connected to an interconnecting structure. Category C is substrates that interconnect uncased or bare chips (i.e., the components of category A) into a separable package. Included here are all types of multichip modules (MCMs), chip-on-boards (COBs), and hybrids. Category D covers all kinds of substrates that interconnect and form assemblies of already packaged components, i.e., those from categories B and C. This category includes all types of rigid PWBs, flexible and rigid-flexible, and discrete-wiring boards. Category E covers the back planes made by printed wiring and discrete-wiring methods or with flexible circuits, which interconnect PWBs, but not components, from the preceding groups. Category F covers all intraenclosure connections. Included in this category are harnesses, ground and power distribution buses, RF plumbing, and co-ax or fiberoptic wiring. Category G includes the system assembly hardware, card racks, mechanical structures, and thermal control components. Category H encompasses the entire integrated system with all its bays, racks, boxes, and enclosures and all auxiliary and support subsystems. As seen from the preceding list, PWBs are exactly in the center of the hierarchy and are the most important and universally used element of electronic packaging. The packaging categories F, G, and H are used mainly in large mainframes, supercomputers, central office switching, and some military systems. Since there is a strong trend toward the use of miniaturized and portable electronic products for the majority of electronic packaging designs, trade-offs are made in the judicious application and selection among the elements of the first five categories. These are discussed in this chapter.
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FACTORS AFFECTING SELECTION OF INTERCONNECTIONS
Selection of the packaging approaches among the various aforementioned elements is dictated not only by the system function, but also by the component types selected and by the operating parameters of the system, such as the clock speeds, power consumption, and heat management methods, and the environment in which the system will operate. This section provides a brief overview of these basic constraints that must be considered for proper packaging design of the electronic system.
Speed of Operation The speed at which the electronic system operates is a very important technical factor in the design of interconnections. Many digital systems operate at close to 100 MHz and are already reaching beyond that level. The increasing system speed is placing great demands on the ingenuity of packaging engineers and on the properties of materials used for PWB substrates.
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