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The importance of the rigorous cost trade-off analysis during the design of electronic products is underscored by the fact that about 60 percent of the manufacturing costs are determined in the first stages of the design process, when only 35 percent of the total design effort has been expended. Attention to manufacturing and assembly requirements and capabilities (so-called design for manufacturability and assembly [DFM/A]) during product design can reduce assembly costs by up to 35 percent and PWB costs by up to 25 percent. The elements that must be considered for the most cost-effective electronic packaging designs are:
Optimization of the PWB design and layout to reduce its manufacturing cost Optimization of the PWB design to reduce its assembly cost Optimization of the PWB design to reduce testing and repair costs
The following sections provide some guidelines on how to approach such optimization of PWB designs. Basically, the costs of the electronic assemblies are directly related to their complexity and there are a number of measurements relating the effects of various PWB design elements to their costs to guide the design engineer in selection of the most cost-effective approach.
ICS AND PACKAGES
The most important factors influencing PWB design and layout are the component terminal patterns and their pitches, especially those of ICs and their packages, since these dictate the density of the interconnecting substrates. Thus, this element will be considered first. Driven by the need for improved cost and performance, the complexity of ICs is constantly increasing. Due to relentless progress in IC technology, the gate density on a chip is increasing by about 75 percent per year, resulting in the growth of IC chip I/O terminals by 40 percent per year, which places ever increasing demands on the methods of their packaging and interconnection. As a result, the physical size of electronic gears keeps shrinking by 10 to 20 percent per year, while the surface area of substrates is being reduced by about 7 percent per year. This is accomplished by continuously increasing wiring densities and reducing linewidths, which has severely stressed PWB manufacturing methods, reduced processing yields, and increased the costs of the boards.
IC Packages Since their inception, IC chips have been placed within ceramic or plastic packages. Until about 1980, all IC packages had terminal leads that were soldered into plated through-holes (PTHs) of the PWBs. Since then, an increasing number of IC packages have their terminals made in a form suitable for surface-mounting technology (SMT), which has become the prevailing method of component mounting. There has been a proliferation of IC package types, both for through-hole assembly as well as for surface mounting, varying in their lead configurations, placement, and pitches. Also, IPC-SM-7823 provides a good catalog of the available SMT packages and of the PWB footprint formats they require for their assembly. Basic I/O termination methods of IC packages include the following:
Peripheral, where the terminations are located around the edges of the chip or package Grid-array, where the terminations are located on the bottom surface of the chip or package
ELECTRONIC PACKAGING AND HIGH-DENSITY INTERCONNECTIVITY
Most IC packages have peripheral terminations at their edges. The practical limit on the peripheral lead pitches on packages is about 0.3 mm, which permits locating, at most, 500 I/Os on a large IC package, as shown in Table 2.2. It has also become evident that, in typical board assembly operations, the yields plummet as the lead pitches go below 0.5 mm.
TABLE 2.2 Various Array Package Body Sizes, Configurations, and Lead Pitches Body size (mm) 8 8 9 9 10 10 13 13 23 23 23 23 23 23 23 23 23 23 27 27 27 27 27 27 27 27 27 27 27 27 31 31 31 31 31 31 31 31 35 35 35 35 35 35 35 35 35 35 37 37 42.5 52.5 52.5 52.5 Number of I/Os 24 68 144 154 168 208 217 240 249 225 256 272 292 300 316 304 329 360 385 313 352 388 420 456 676 1247 2577 Minimum pitch (mm) 0.5 0.5 0.5 0.65 1.27 1.27 1.27 1.27 1.27 1.27 1.27 1.27 1.27 1.27 1.27 1.50 1.27 1.27 1.27 1.27 1.27 1.27 1.27 1.27 0.8 1.0 1.0
Various area array components come with a large variety of body sizes, numbers of I/Os, and I/O pitches. These components are called chip-scale packages (CSPs), plastic ball grid arrays (PBGAs), ceramic ball grid arrays (CBGAs), plastic pin grid arrays (PPGAs), and ceramic column grid arrays (CCGAs).
It is expected that chips with terminal counts below 150 to 200 will continue to use packages with peripheral leads, if these can be soldered within practical assembly yields. But for IC packages with over 150 to 200 I/Os, it is very attractive to use the grid-array terminations, since in such a case the entire bottom surface area can be utilized for terminations, which makes it possible to place large numbers of I/Os within a limited area. This consideration has led to the development of a number of area array solder-bumping termination methods for IC and multichip module (MCM) packages, variously called pad grid, land grid, or ball grid arrays (BGAs) with terminal grids set at 1 mm (0.040 in), 1.27 mm (0.050 in), and 1.50 mm (0.060 in), respectively. Use of grid arrays provides a number of benefits. The most important is the minimal footprint area on the interconnecting substrate, but grid arrays also offer better electrical performance due to low electrical parasitics in high-speed operation, simplified adaptation into SMT
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