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TABLE 19.2 Typical Layout Efficiencies Design scenario Through hole, rigid Surface mount/mixed Surface mount/mixed Surface mount only Surface mount/mixed Surface mount/mixed Built-up technologies Conditions Gridded CAD W/wo back side passives, gridless CAD W/back side actives, gridded CAD W/wo back side passives, gridless CAD 1-sided blind vias, gridless CAD 2-sided blind vias, gridless CAD 2-sided micro-blind vias, gridless CAD Efficiency* (%) 6 12 8 15 9 18 Up to 20 Up to 25% Up to 30 Up to 50%
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* Determined from analysis of printed circuit designs (actual wiring capacity from the CAD system divided by maximum wiring capacity (Eq. 19.4).
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19.4.5.1 Wiring Demand Models. Seven wiring models are reported in the literature, but the first three are used commonly. The three wiring models include:
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Coors, Anderson & Seward Statistical Wiring Length4 Toshiba Technology Map5 Hewlett Packard (HP) Design Density Index6
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The other four wiring models include:
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Equivalent ICs per square inch7 Rent s Rule8 Section Crossing9 Geometric Analysis10
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19.4.5.1.1 Coors, Anderson, & Seward Statistical Wiring Length. This wiring demand model is based on a stochastic model of wiring involving all terminals. The probable wire length is calculated based on the distance of a second terminal and the spatial geometry of all other terminals. This is the most recently determined wiring model and represents the most practical approximation of surface mounting technology. Eq. 19.5 presents the mathematical model that results. d = D * Ni/A (in. per sq. in.) where D = ave. interconnection distance (in.) D = E(x)*G E(x) = expectation of occurrence G = pad placement grid (in.) Ni = total number of interconnections A = routing area (sq. in.) (19.5)
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Equation 19.6 for E(9x) is the E(x) = 1 ((S T )(S a 2))e^aS + S(2 (S T )a)e^ a(S T ) 2T a (S T )e^aS Se^a(S T ) + T (19.6)
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45 0
CH IN
80 59 56 52 51 47 33
Component Density (parts / sq. inch)
LE AD S
A DE SSE NS M IT BLY Y
PE R
0 32
SQ .
IN CH
23 19 18 15
23 25 16 13 9
25 0
(19 96 )
LE AD S
PE R
SQ .
LE AD S
PE R
13 11
SQ .
INC H
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CH IN
R PE . SQ CH IN
INC H
R PE SQ . CH IN 6) 99 (1
9 8 6 6
0 16
CH IN R PE SQ .
B ITY PWENS D
CH IN
1 1 10 100
Component Complexity (ave leads / part)
FIGURE 19.11 Packaging technology map.
where
S T a a M N Ni
=M+N = (M^2 + N^2)^.5 = ln a = empirically derived constant = 0.94 = board width of grid point = (width/G) +1 = board length of grid point = (length/G) +1 = 2*Nt/3
19.4.5.1.2 Toshiba s Technology Map. The packaging technology map is a simple technique to predict a PWB, Chip-On-Board, or MCM-L wiring demand and its assembly complexity. By plotting components per square inch (or components per square centimeter) against average leads per component on a Log-log graph (see Fig. 19.11), you can calculate the wiring demand WD in inches per square inch (or centimeters per square centimeters) and assembly complexity in leads per square inch (or leads per square centimeter). Eqs. 19.7 and 19.8 show the equations for these two metrics. Wiring Demand WD = b (comp)0.5 (leads) where b = wiring coefficient (typically 3.5 but can vary from 2.5 4.0 on average; notes/net is a good approximation) comp = components per board area in sq. in. or sq. cm. leads = average leads (connections) per component Assembly Complexity = (comp) (leads) comp = components per board area in sq. in. or sq. cm. leads = average leads (connections) per component (19.8) (19.7)
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Parts per Sq. Inch 100
Actual Wiring Connectivity: In./Sq.In.
Leads/Sq.In.
50 70 100 200 300 60 80 120 160 180 240 320
in./sq.In.
Packaging Density: Leads/Sq.In.
FIGURE 19.12 Wiring and assembly density.
10 Ave Leads per Part
Using these two equations, Fig. 19.12 shows lines of constant wiring demand (in cm. per sq. cm or in. per sq. in.) and assembly complexity (in leads per sq. cm. or sq. in.) that can be plotted on this chart (see Fig. 19.11). 19.4.5.1.3 HP s Design Density Index. Another metric is called the Design Density Index (DDI). It is a correlation of the actual design rules for a PWB compared to the DDI metric. Equation 19.9 gives DDI, and Fig. 19.13 shows a typical calibration chart. DDI = 13.6 (EIC/board area)^1.53 where EIC (equivalent integrated circuits) = total component leads/16 board area = top surface area of a PCB (sq. inch.) (19.9)
The chart shown in Fig. 9.13 gives a good visual record in PWB layout of a company s efficiency. As various PC boards are charted, their DDIs form a distribution. This distribution is a form of layout efficiency (e) since at the bottom of the distribution, more EICs are connected than at the top of the distribution. 19.4.5.1.4 Density of Equivalent ICs. EIC per unit area has been a traditional measure of density since the introduction of CAD systems in the early 1970s. A simple measure of the number of electrical connections required per unit area of the board, it remains in use with
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