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Component Density Analysis Because the components and their terminations exert a major effect on the design of the PWB, a number of metrics have been developed to establish the relationships between component density and PWB density.A major analysis of these relationships has been made by H. Holden5 and some of his charts and derivations are provided here to guide the design engineers during the development of a rational PWB design. This information is very useful in determining where the designed product will fit in the component density spectrum and what, therefore, is to be expected for PWB density. Figure 2.7 provides a generalized view of the relationships among the component density, their terminal density, and the necessary wiring density that will be required to accommodate the selected degree of component complexity. The definition of the wiring connectivity Wf is provided.
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FIGURE 2.7 Plot of general relations between component and wiring density.
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PWB Density Metrics It is essential for the proper design of PWBs to determine the density requirements and then analyze alternative methods of board construction for the most cost-effective design. There are a number of basic terms and equations used for the calculation and analysis of PWB wiring density.
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ELECTRONIC PACKAGING AND HIGH-DENSITY INTERCONNECTIVITY
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Wc = where Wc = T= L= G= wiring capacity tracks per channel number of signal layers channel width
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T*L in/in2 G
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(2.1)
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But it is more important to determine the required wiring density that will be sufficient to interconnect all the components on the desired board size. There have been a number of empirically developed equations that permit the calculation of such a wiring demand. The simplest has been developed by Dr. D. Seraphim:6 Wd = 2.25 Nt*P where Wd = wiring demand Nt = number of I/Os P = pitch between packages 2.6.3 Special Metrics for Direct Chip Attach The assembly of uncased or bare chips on substrates has become popular mostly due to the ability of such assemblies to reduce the area of interconnections. The ideal limit for such assembly would be to place all the chips tightly together, without any space in between. This would result in 100 percent packaging efficiency, a metric measuring the ratio of silicon area to the substrate area. Naturally, such 100 percent efficiency is not achievable, but this metric is still useful in ranking various substrate construction or bare chip attachment methods, as shown in Fig. 2.8. (2.2)
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FIGURE 2.8
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Packaging efficiency. (Courtesy of BPA, used with permission.)
Packaging efficiency of 100 percent is impossible to achieve because all chip-mounting methods require some space around the chips. Even with flip-chips, there must be a distance left between the chips to permit room for the placement tool.
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FIGURE 2.9 Chip area required to accommodate bonding methods.
Dr. H. Charles7 of Johns Hopkins University has listed the dimensions in Table 2.3 for the necessary spacing between the chips (or the total width of the frame around the chips) for various chip attachment methods. These or very similar distances have also been cited by a number of other sources. Even with the flip-chip mounting, packaging efficiency must be derated to about 90 percent, for wire-bonding to 70 percent and for TABs to about 50 percent, and in some cases much more. A very similar situation is shown graphically in Fig. 2.9. The packaging efficiency deratings shown in Fig. 2.9 are required to accommodate only the wiring bond pads on the substrates. But the mounting of bare chips on PWBs requires additional signal redistribution area to permit placement of larger-diameter PTHs farther out for communication with internal layers. It is evident that the packaging efficiencies on PWBs could be reduced to the range of only 20 to 30 percent, unless special surface signal redistribution layers (as previously mentioned) are used, which are made of unreinforced dielectric material. In such cases, packaging efficiency and the chip-to-chip distances will again be similar to the values cited in Table 2.3.
TABLE 2.3 Spacing Required Between Chips Attachment method Flip-chip Wire-bonding Flip TAB Regular TAB Chip spacing, mils 15 20 70 80 100 120 150 400
It is apparent that direct chip attach on PWBs will result in the significant reduction of the packaging efficiency of such assemblies, except for the fact that components can be mounted on both sides of the PWB substrate. It has been shown that wire-bonding can be done on both sides of a PWB with some special fixturing; also, outer lead bonding (OLB) of TABs can be done on both sides of the PWB substrate. Thus, while single-sided bare chip assembly on PWBs reduces its packaging efficiency to about half that of other types of substrate constructions, the ability to place components on both sides of PWBs brings it back to the same packaging efficiency level as others.
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