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TABLE 19.6 Example of ExcelTM Transformation Setup for Complexity and Yield Data Complexity X1 1144136 2006116 14909 546435 162158 2167611 8002482 4773612 5604279 10848424 64014 12737 2716 1144136 2006116 14909 546435 162158 *** 64014 12737 2716 YIELD Y 92.6 85.6 95.6 92.3 94.8 86.8 90.3 89.3 87.2 86.6 92.7 93.8 99.2 84.9 85.7 93.9 93.3 97.6 *** 96.6 95.6 99.3 Log-log (x1) 0.78 0.80 0.62 0.76 0.72 0.80 0.84 0.82 0.83 0.85 0.68 0.61 0.54 0.78 0.80 0.62 0.76 0.72 *** 0.68 0.61 0.54 Log in Log-log fit ( Y/100) all data 1.11 0.81 1.35 1.10 1.27 0.85 0.99 0.95 0.86 0.84 1.12 1.19 2.10 0.78 0.81 1.20 1.16 1.62 *** 1.46 1.35 2.13 AVG Error STD DEV 90.6 89.4 97.0 92.0 94.1 89.2 86.1 87.4 87.0 85.3 95.4 97.2 98.4 90.6 89.4 97.0 92.0 94.1 *** 95.4 97.2 98.4 Error all data 2.0 3.8 1.4 0.3 0.7 2.5 4.2 1.9 0.2 1.3 2.7 3.4 0.8 5.7 3.7 3.1 1.3 3.5 *** 1.2 1.6 0.9 Log-log fit avg. only 90.1 88.9 96.7 91.5 93.6 88.7 85.6 86.9 86.5 84.8 95.0 96.9 98.2 90.1 88.9 96.7 91.5 93.6 *** 95.0 96.9 98.2 Error avg. only 2.5 3.3 1.1 0.7 1.1 1.9 4.7 2.4 0.7 1.8 2.3 3.1 1.0 5.2 3.2 2.8 1.7 4.0 *** 1.6 1.3 1.1
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19.5.2.5 Calculating the Board Complexity Index and Average Yield: Regression Analysis Methodology. To determine the constants A and B in Eq. 19.12, you can use any statistical software program that has a model-based regression analysis.The model is shown in Eq.19.13. Table 19.6 shows an example of an ExcelTM spreadsheet setup, and Table 19.7 shows the regression results.
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TABLE 19.7 Example of ExcelTM Regression Results All data Log-log fit FIT Sig-M R2,sig-B F, df Reg sum sq B A slope 3.17 0.18 0.73 312.60 11.01 3.17 12.57 int. 3.48 0.13 0.19 115 4.05 AVG only slope int. 3.06 0.34 0.88 81.75 1.14 3.06 12.66 3.38 0.25 0.12 11 0.15
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TABLE 19.8 Example of One Company s Fabrication Complexity Matrix Fabrication factors Material of construction No. of layers No. of holes/ panel Min. Trace/spacing Gold tabs Annular ring Solder mask Metalization High middle BT 8 layers 10,001 20,000 3 4 mil. 2 Sides 2 4 mil. 2 S LPI Selective lead-free solder coat 9 12 mil. +/ 10 % Low middle FR-4 4 layers 3001 10000
Pts. 147 196 270 25 48 30 25 75
Highest Polyimide 12 layers <20,001 2 mil. 3 Sides >2 mil. 2 S Dry Film Electroless Ni/Au <= 8 mil. +/ 5 %
Pts. 88 137 180 10 32 21 17 69
Pts. 49 89 90
Pts. 40 36 27
Lowest CEM III 2 sided >3000
16 7 46
5 6 mil.
1 Side 4 6 mil. 1 S LPI Immersion silver 13 20 mil. +/ 20 %
0 1 5 29
<=6 mil.
None <6 mil. Screened SMOBC/ organic coat <20 mil. None
Min. hole dia. Controlled impedance tolerance
166 105
84 62
69 30
Points are per PANEL
For board: Divide by no. per PANEL
19.5.3 Example of a Complete PWB Complexity Matrix This section presents an example of how one company approached this planning process as part of its PWB design for manufacturing program. 19.5.3.1 PWB Fabrication Complexity Matrix (FCM). The PWB fabrication complexity matrix that this company developed is shown in Table 19.8. This FCM is built on a per panel basis of 18 in. by 24 in. rather than a per board basis. Also, volume is assumed to be in a preset amount. 19.5.3.2 PWB Complexity. Figure 19.14 shows this company s first-pass yield. The curve with A = 11.5 and B = 9.0 was current for six months. Price index is the total points from the complexity matrix divided by the first-pass yield. 19.5.3.3 Relative Costs. The price index data for this company is shown in Fig. 19.15. The price index (PI) can vary from 150, which corresponds to a 70 percent price reduction, to a PI of 1,000 which corresponds to a 275 percent increase in price. 19.5.3.4 PWB Fabrication Example. Let s continue with the consumer electronics board example from Sec. 19.4.5. Table 19.9 lists the initial design characteristics of the printed circuit and the resultant total design points. Table 19.10 shows the calculation of the complexity index, estimated first-pass yield, and resultant price index and price adjustment. The wiring demand indicates that a 0.007 in trace and a 0.008 in spacing(two track) for a 0.100 in grid (channel) represent more density than is required (see Sec. 19.4.5). A one-track wiring on two signal layers could achieve the required wiring density or a 0.012 in trace
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