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DFM Enhancements The manufacturability of the PCB can be improved through design enhancements. Many of the enhancements can be performed on CAD systems (or through specialized post-CAD software); other enhancements can be performed at the manufacturing site. Ideally, all design enhancements would be performed at the design site to maintain the consistency of products from multiple manufacturers; however, some of the DFM enhancements can impact the CAD system s capability to provide further design changes. Specifically, the optimization of track-to-feature spacing could result in blocked routing channels, preventing an autorouter from performing. The following are typical DFM enhancements (see Fig. 20.15): Item Copper balancing Result from enhancement The balancing of copper on the surface of the design will improve the distribution of plating (in the pattern-plating process), preventing areas of overplating due to the isolation of features. This improvement enables the manufacturer to control the plated hole diameters to tolerances and reduce plating heights, which impact solder mask coverage. (See Fig. 20.15a.) As annular rings decrease due to tighter design specifications, the probability of defects occurring due to registration/annular ring failures increases. The addition of teardropping increases the pad-to-trace junction size, improving the reliability of the connection and improving product yields.(See Fig. 20.15b.) Innerlayer shorts result from several factors, among them the proximity of circuitry to other circuitry. The occurrence of shorts can be correlated to the running length of the circuitry versus the running length at some minimum spacing between circuitry (at the process capability of the operation). Reducing the total distance at minimum spacing will reduce the probability of shorts, resulting in improved yields. (See Fig. 20.15c.) As described in the nonfunctional pads discussion, the occurrence of shorts can be correlated to the running length of the circuitry versus the running length at some minimum spacing between circuitry (at the process capability of the operation). Reducing the total distance at minimum spacing will reduce the probability of shorts, resulting in improved yields. (See Fig. 20.15d.) The occurrence of opens can be correlated to the running length of the circuitry versus the running length at minimum track width (at the process capability of the operation). Reducing the total distance at minimum track width will reduce the probability of opens, resulting in improved yields. (See Fig. 20.15e.)
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Removal of nonfunctional pads on innerlayers
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FIGURE 20.15 Typical producibility problems created in design.
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Panelization In the panelization process, the PCB single images are placed in the locations defined in the panelization definition step of the initial design review. In addition, the following features may be added to the panel for manufacturing: Item Customer coupons Purpose These coupons are provided to the customers for their inspection of the PCB product. These coupons are typically treated as separate PCB single images. During the manufacturing process, destructive testing may be required to confirm product quality. These coupons are typically treated as separate PCB single images. Holes used for registration of manufacturing panels to artwork, drilling, or routing operations are added to the panel borders. Plating thieving patterns are sometimes needed to balance the platable area across the panel. The addition of copper to innerlayers outside the PCB single image provides more consistency in the lamination process. Operator aides may be provided outside the PCB single image to improve manufacturing quality.
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Tooling holes
Outerlayer thieving patterns Innerlayer venting patterns
Textual markings
Fabrication and Assembly Parameter Extraction Additional manufacturing information must be extracted or calculated from the design file before fabrication or assembly can begin.This information is loaded and stored in several files
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and databases used to run various fabrication and assembly equipment. In addition to requiring the basic tooling steps already defined, most PCB manufacturing sites also require the designer to provide the following information:
Raw materials shearing and labeling instructions Copper foil thicknesses and etch rates Automatic optical inspection files Lamination lay-up BOM and order/stack height Lamination press cycles, heat input, and pressure settings Drill-file location and revision levels Plating area calculations and current density settings Copper foil thicknesses and etch rates Router-file location and revision levels Electrical test programs Quality control procedures and coupon disposition Final packing and shipping instructions
20.6.6.1 AOI Files. The CAD reference files, if required, are generally created at the PCB manufacturing site. These files prepare automated optical inspection (AOI) systems with data that confirm that manufactured pieces match, within tolerances, the PCB design. 20.6.6.2 Lamination Parameters. Each multilayer stack-up and material may require specific lamination processes. Modern multilayer presses have microprocessor-controlled time, temperature, and pressure. These parameters require selection in the tooling process. 20.6.6.3 Drill Files. Drill files and the respective drill bit tools must be archived and available for download to the appropriate drilling machine when production needs them. Drill bit preparation precedes the actual drilling operation in order to create the drill cassette. 20.6.6.4 Plating Coefficients. Plating requires specific direct currents (DC) to be applied to this part. The current density of the appropriate plating bath is multiplied by the plated area on each production rack. After the first actual run, direct measurement of the plated metals is used to adjust the plated area to achieve the correct thicknesses. 20.6.6.5 Routing Files. Router files and the respective router cutting tools have to be archived and available for download to the appropriate routing machine when production needs them. Router tool preparation precedes the actual routing or secondary drilling operation in order to create the final fabrication cassette. 20.6.6.6 Electrical Test Programs and Fixture Creation. An electrical test netlist file may be either created internally from the artwork or prepared from a supplied IPC-D-356 file.This test file has to be compared to the netlist extracted from the artwork supplied. Any difference must be resolved before the actual electrical test file is finalized. In addition, the electrical test fixture must be constructed or sent to an outside contractor to prepare. 20.6.6.7 CAD to Assembly Processes. The assembly tooling operations include CAD interfacing to component data and BOM. These operations include the generation of manufacturing documentation (see Fig. 20.16) and assembly engineering for component machine management, program optimization, and line balancing (see Fig. 20.17).
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