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FIGURE 2.11
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Yield loss from shorts.
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PRINTED CIRCUITS HANDBOOK
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A useful empirical equation for calculating the manufacturing cost is: Cost C = (material + process costs) Yield Y (2.3)
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To establish the effect of the interconnection density Id on the final yield of substrates, the total processing yield can be split into two components: one that depends on the conductor density, i.e., YId, and the second, which is a function of the combined yields of the rest of the manufacturing processes: Ytotal = YId*Yproc (2.4)
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In a well controlled manufacturing operation, the process-dependent yields (such as plating) remain fairly constant for a given technology, permitting the yield function to be based solely on the changes in the conductor widths.
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FIGURE 2.12 widths.
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Cost relationships between number of layers and conductor
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ELECTRONIC PACKAGING AND HIGH-DENSITY INTERCONNECTIVITY
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As seen from Fig. 2.11, the defects that affect this density-dependent yield function YId are conductor opens and shorts between them. It would be reasonable to assume that such defects have a Poisson distribution over the total length TL of conductors of a substrate, with an average defect frequency of v. The yield is the probability of zero defects (n = 0) in the total conductor length TL. Thus, Y = (at n = 0) = e( n*TL) (Poisson distribution) (2.5)
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As seen from Figs. 2.10 and 2.11, the defect frequency n depends also on the widths of lines and spaces, i.e., on the conductor pitch Cp. With a decrease of Cp, n will increase, but for very large Cp, n should be 0, since YId will be 100 percent. For instance, in the case of a design using invisible pads, where Cp = 2w, the interconnection density Id can be expressed as Id = TL/A, and Id is proportional to Cp, i.e., Id * Cp = 1, and TL = A/Cp. Therefore, n in this equation can be empirically expressed as: n = ln Y0 Cp0 * TL0 Cp
(2.6)
where b is an exponent dependent on the technology or process used to form the conductors. This exponent b varies considerably from facility to facility and among various pattern formation methods, and must be empirically determined for each case. 2.7.4 Increase in Number of Conductor Layers This is the simplest and most straightforward solution: when there is insufficient room on existing layers to place all the necessary interconnecting paths, add a layer. This approach has been widely practiced in the past, but when cost effectiveness of the substrates is of paramount importance, a very careful design analysis must be made to minimize layer counts in MLBs, because there is a significant cost increase with every additional layer in the board. As seen from Table 2.6, calculated for 6- 8-in MLBs produced in large quantity with yields and conductor density kept constant, there is almost a linear relationship between board costs and layer count. Table 2.6 also shows that any increase in the number of signal layers in boards operating at frequencies requiring transmission line characteristics will double the total number of layers, due to the need to interleave ground or DC power planes between signal planes. A typical example of the effect of layer count on the finished MLB yield can be seen from Fig. 2.12, prepared some years ago by BPA. We can see that there is a definite decrease in the manufacturing yields with an increased number of layers in any of the linewidth categories. This is rather a typical situation in board manufacturing because increased complexity and thickness of MLB with a higher number of layers usually leads to a larger number of problems on the production floor.
REFERENCES
1. Toshiba, New Polymeric Multilayer and Packaging, Proceedings of the Printed Circuit World Conference V, Glasgow, Scotland, January 1991. 2. The Institute for Interconnecting and Packaging Electronic Circuits, 7380 N. Lincoln Ave, Lincolnwood, IL 60646. 3. IPC-SM-782, Surface Mount Design and Land Pattern Standard, The Institute for Interconnecting and Packaging Electronic Circuits. 4. Y. Tsukada et al., A Novel Solution for MCM-L Utilizing Surface Laminar Circuit and Flip Chip Attach Technology, Proceedings of the 2d International Conference on Multichip Modules, Denver, CO, April 1993, pp. 252 259.
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