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channels that are then filled with a conductive ink. These approaches eliminate the need for a separate dielectric and clad-metal layer that requires either etching or a combination of plating and etching to produce a circuit. They also eliminate the resist deposition and stripping previously required to define that circuit. The conductive ink technique of metallization virtually eliminates the generation of metal waste streams. Conventional multilayer printed wiring boards must be subjected to drilling and throughhole plating to create interconnections. These holes represent inefficient use of PWB area. In addition, to connect the printed wiring with part connection lands, some through holes must be provided in areas other than where the lands are located.
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1. Bauer, Charles E., and Bold, William A., Tektronix, Inc., U.S. Patent 4,566,186, Multilayer Interconnect Circuitry Using Photoimageable Dielectric, January 28, 1985. 2. Tsukada, Y., and Tsuchida, S., Surface Laminar Circuit, A Low Cost High Density Printed-Circuit Board, Proceedings of the Surface Mount International Conference and Exposition, San Jose, CA, September 1992. 3. Schmidt, W., A Revolutionary Answer to Today s and Future Interconnect Challenges, Proceedings of the Sixth PC World Conference, San Francisco, May 1993. 4. Holden, H., Segmentation of Assemblies: A Way to Predict Printed Circuit Characteristics, Proceedings of IPC T/MRC, New Orleans, December 6, 1994. 5. Holden, H., IPC-2315, Design Guidelines for HDI and Microvias, IPC, 1998, pp. 55. 6. Holden, H., The Challenge: To Plan Successful Products When Packaging Is So Complicated, Future Circuits, Vol. 2, No. 1, 1997, pp.106 109. 7. Seraphim, D. P., Lasky, R. C., and Li, C.Y., Principles of Electronic Packaging, McGraw-Hill, 1989, pp. 39 52. 8. Heller, W. R., His, C. G., and Mikhail, W. F., Wireability: Designing Wiring Space for Chips and Chip Packages, IEEE Design Test, August 1984, pp. 43 51. 9. Sweetman, E., Characteristics and Performance of PHP-92: AT&T s Triazine-Based Dielectric for Polyhic MCMs, International Journal of Microcircuits and Electronic Packaging, Vol. 15, No. 4, 1992, pp. 195 204. 10. Gonzalez, Ceferino G., Materials for Sequential Build-Up (SBU) of HDI-Microvia Organic Substrates, , The Board Authority, June 1999, pp 56 58 11. Circuit Tree HDI Materials, The Board Authority Journals on HDI, June 1999 and April 2000, CircuiTree magazine, BNP Publishing. 12. Bakoglu, H. B., Circuits, Interconnections and Packaging for VLSI, Addison Wesley, 1990. 13. Hannemann, R. J., Introduction: The Physical Architecture of Electronic Systems, Physical Architecture of VLSI Systems, R. Hannemann, A. D. Kraus, and M. Pecht (eds.), John Wiley & Sons, 1994, pp. 1 21. 14. Moresco, L., Electronic System Packaging: The Search for Manufacturing the Optimum in a Sea of Constraints, IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. 13, 1990, pp. 494 508. 15. Maliniak, D., Future Packaging Depends Heavily on Materials, Electronic Design, January 1992, pp. 83 97. 16. Powell, D., and Weinhold, M., Laser Ablation of Microvia Holes in Woven Aramid-reinforced PWBs, Chip Scale Review, September 1997, pp 38 45. 17. Poulin, D., Reid, J., and Znotins, T. A., Materials Processing with Excimer Lasers, International Congress on Application of Lasers and Electro-Optics (ICALEO) paper, November 1982. 18. Knudsen, P. D., et al., U.S. Patent 5,262,280, November 16, 1993. 19. Shipley, C. R., U.S. Patent 4,902,610, February 20, 1990.
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20. Shipley, C. R., U.S. Patent 5,246,817, September 21, 1993. 21. Sakamoto, Kazunori, Yoshida, Shingo, Fukuoka, Kazuyoshi, and And , Daizo, The Evolution and Continuing Development of ALIVH High-Density Printed Wiring Board, presented at IPC Expo 2000; featured in Circuit Tree, May 2000, pp 34 37. 22. Itou, Motoaki, High-Density PCBs Provide for More Portable Design, http://www.nikkeibp.com/ nea/nov99/tech/. 23. Microvia Substrates: An Enabling Technology for Minimalist Packaging 1998 2008, BPA Group Ltd., 1999, pp. 4 3 to 4 17. 24. Tsukada, Yutaka, et al., Surface Laminar Circuit and Flip Chip Attach Packaging, Proceedings of the Seventh IMC, 1992. 25. Tsukada, Yutaka, Introduction to Build-Up Printed Wiring Board (in Japanese), Nikkan Kogyo Shinbun, 1998. 26. Holden, Happy, Special Construction Printed Wiring Boards, Printed Circuit Handbook, 4th ed., Clyde F. Coombs, Jr. (ed.), McGraw-Hill, 1995, chap. 4. 27. Takahashi, Akio, Thin Film Laminated Multilayer Wiring Substrate, JIPC Proceeding, Vol. 11, No. 7, November 1996, pp. 481 484. 28. Shiraishi, Kazuoki, Any Layer IVH Multilayer Printed Wiring Board, JIPC Proceeding, Vol. 11, No. 7, November 1996, pp. 485 486. 29. Fukuoka, Yoshitaka, New High Density Printed Wiring Board Technology Named B2it, JIPC Proceeding, Vol. 11, No. 7, November 1996, pp. 475 478. 30. Apol, Tim, Directional Plasma Etching Straight Sidewalls, No Undercut, PC Fabrication, Vol. 20, No.12, December 1997, pp. 38 40. 31. Tsuyama, Koichi, et al., New Multi-Layer Boards Incorporating IVH: HITAVIA, Hitachi Chemical Technical Report, No. 24, 1995-1, pp. 17 20. 32. Tokyo Ohka Company Brochure.
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