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FIGURE 23.12 The fabrication process for carrier-formed circuit multilayer substrate.
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FIGURE 23.13 A typical high-density CLLAVIS.
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Repeat steps 1 6 for the remaining cores of the multilayer 7. 8. 9. 10. Lay up the finished cores with copper foil. Vacuum laminate the finished layers. Image and circuitize the outer layers Coat the solder mask and finish. This process can be seen in Fig. 23.15.
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FIGURE 23.14 The typical manufacturing process for CLLAVIS boards.
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FIGURE 23.15 The typical manufacturing process for SSP boards.
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FIGURE 23.16 The typical manufacturing process for FACT-EV boards.
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23.3.2.5 FACT-EV. FACT-EV (Fujikiko Advanced Chemical Technology-Etched Via Post) is from Fujikiko of Japan. As with the SSP process, the via is a solid-plated copper post. In this case, the process uses standard dry-film photoresist to define the posts and a thin-liquid dielectric to coat the plated posts. Unlike SSP, however, the process is sequential and each two sets of layers are processed on the prior layers. The process is outlined in Fig. 23.16. 23.3.2.6 PPBU. The PPBU (Prepreg Build-Up), from CMK, is a standard sequential lamination process using laser-drilled vias similar to the CLLAVIS process. The diagrams in Fig. 23.17 show two of the structures, a standard 2+4+2 build-up and an advanced 3+2+3 stacked build-up. 23.3.2.7 Solid Conductive Via Fill. The next group of HDI technologies all utilize metallic copper pastes or a solid sheet of metal to form the via connections. Table 23.1 presents these alternatives to copper plating for forming IVH connections. 23.3.2.8 OrmeLink. CTS s co-lamination process and Ormet s transient liquid phase sintering (TLPS) process (OrmaLink) are similar to the ALIVH process conductive paste in that it is a via paste copper-tin organometallic matrix that sinters into a solid metallurgical via.
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FIGURE 23.17 The typical manufacturing process for FACT-EV boards.
CTS s process is called ViaPly. Past users, in addition to Sheldahl, included Litronics, now called Allied-Signal Substrates, in Costa Mesa, California. Up to four layer pairs have been connected (eight metal layers) using OrmeLink. 23.3.2.8.1 Structure. The Ormet structure is made up of polyimide or FR-4 layer pairs. Different materials can be mixed if a rigid core or heat spreader is required. The conductive paste is a TLPS ink of copper-tin. The structure is shown in Fig. 23.18. Figure 23.19 shows the cross-sections of two finished circuits with lasered-via polyimide layer pairs, with TLPS solid metallurgical vias connecting the layer pairs and FR-4 innerlayer cores with buried TLPS vias. 23.3.2.8.2 Manufacturing Process. The manufacturing process is shown in Fig. 23.20. The microvias are lasered or punched in the polymide adhesive and then filled with the TLPS paste. The structure can now take layer pairs from any other HDIS process (such as Sheldahl s) and turn them into a multilayer structure through sintering. The conductive pastes have to be sintered in a condensing vapor of fluorocarbon at 215 C for 2 min. The structure is then postcured by baking for 40 min. at 175 C. Table 23.2 details the process.
TABLE 23.1 Alternative HDI Technologies Fabricator Dyconex Ormet Matsushita Comp. Toshiba Parelec Namics North Corp. Denso Ibiden Fujikiko Trade name DYCOre OrmeLink ALIVH Bbit PARMOD Unimec NMBI NMTI (Neo-Manhattan) PALUP SSP Fact-Ev IVH process Copper etching Laser,plasma,or photodielectric Laser Insulation displacement Drill, laser, or photodielectric Punch, drill Image and etch Laser Laser Photoprocessing Metalization Etched copper bumps Cu/Sn organo-metallic Copper particles in epoxy Silver/epoxy paste Metallo-organic decomposition, Cu or Ag Silver, palladium, and copper particle pastes Etched copper bump Cu organo-metallic Plated copper bumps Plated copper posts
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FIGURE 23.18 The co-lamination (OrmeLink) multilayer structure.
FIGURE 23.19 Examples of TLPS cross-sections of three layer pairs with lasered-vias filled with TLPS paste vias and buried vias for FR-4 innerlayers.
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FIGURE 23.20 The OrmaLink multilayer substrate fabrication process.
TABLE 23.2 Properties and Curing Processes for the Ormet Type of TLPS Conductive Pastes Property Ormet 2005 series ink Electrical conductivity Adhesion (Tensile Pull) on Various Materials FR-4 (Tg = 125 C) Copper Printability Curing process Specification and processing parameter Bulk 4.0 10 3 Ohms-cm. Sheet resistance 10.0 10 3 Ohms/sq. in. 1,300 psi (minimum) 2,921 psi (average) With 230 stainless steel wire mesh and emulsion thickness of 7.5 m Sintered thickness 28 38 m 200 m traces on 400 m pitch 30 min. drying at 85 C 2 min. vapor cure at 215 C 40 min. postcure at 175 C
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