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FIGURE 3.4
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Integrated circuit packaging trends.
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are 0.060 in or less (i.e., 0.050 in, 0.5 mm, 0.4 mm, 0.3 mm). Array-type packaging concepts have emerged to provide higher package electrical performance and/or lower packaging densities (package area/die area).
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Dual Inline Packages (DIPs) Figure 3.5 shows the configuration of a DIP. DIPs are available with a cofired ceramic body with the leads brazed along the long edges or in a postmolded construction where the die is bonded to a lead frame and gold wires interconnect the chip to the lead frame leads prior to molding of a plastic body around the lead frame. DIPs are limited to 64 or fewer I/Os.
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FIGURE 3.5 Dual inline package.
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Leadless Ceramic Chip Carriers To improve the form factor, packages for commercial and military applications were developed called leadless ceramic chip carriers, consisting essentially of the cavity portion of the ceramic hermetic DIP (see Fig. 3.6) with solderable lands printed onto the bottom of the leadless ceramic chip carrier package. These parts were assembled on ceramic substrates and used in both military and telecommunications products. Almost concurrently, leaded versions of the leadless packages begin to appear. The pitches of the leadless parts were 0.040 and 0.050 in, while the leaded parts were on a 0.050-in pitch. Reference 3 discusses these developments in detail. By 1980, thrust-to-quad surface-mount packaging had begun, with the emphasis on leaded plastic quad packages. Reference 4 shows that by 1993 there was a dramatic swing away from through-hole-mounted parts (i.e., DIPs) to surface-mount packages. In 1993, 50 percent of the semiconductor
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SEMICONDUC TOR PACKAGING TECHNOLOGY
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packages fabricated were through-hole-mounted DIPs. By 2000, this percentage dropped to 30 percent, and by 2005 it is projected to drop to only 15 percent. 3.2.3 Plastic Quad Flat Package (PQFP)
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FIGURE 3.6 Leadless ceramic chip carrier.
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The driver for the surface-mount plastic packages has been the development of the plastic quad flat package (PQFP), which consists of a metal leadframe with leads emanating from all four sides. The leadframe is usually copper, to which the semiconductor die is die bonded (usually epoxy die bonded). The I/Os of the die are connected by wire bonds to the leadframe leads.The conventional method of wire-bonding is thermosonic gold ball wedge bonding. A plastic body is then molded around the die and the leads are trimmed and formed. Figure 3.7(a) shows a cross-sectional view of a PQFP. PQFPs have their leads formed in a gull-wing fashion (see Fig. 3.7), while PLCCs have their leads in the shape of a J, which are formed (i.e., folded) underneath the package. Figure 3.8 shows the lead pitch and pin count limit versus QFP size and lead pitch. QFPs are in production and readily used in the assembly of product with 0.5-mm pitch. Based on molding capability and impact of lead length on electrical performance,
FIGURE 3.7 Surface-mount plastic package types.
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a molded body 30 mm on a side is thought to be the practical limit. QFPs with 0.5-mm pitch based on the preceding are limited to around 200 I/Qs. QFPs with 0.4-mm pitch have been implemented.
FIGURE 3.8 Lead pitch and pin count limit vs. QFP size and lead pitch.
Figure 3.7 shows the variety of surface-mount plastic packages that have been developed based on PQFP technology. Ceramic and plastic QFPs, as well as PLCCs, are used to package gate array and standard cell logic and microprocessors. Small-outline IC and small-outline J-lead packages are used to package memory (SRAM and DRAM) as well as linear semiconductors. Pin count for all package types is limited only by molding capability and the demand for ever thinner molded packages.
Pin Grid Array (PGA) and Pad Array Carrier (PAC) Consider the impact of using a perimeter I/O package versus an area array package. Figure 3.9 illustrates the differences between a perimeter array package (leadless chip carrier) and an area array package (PAC). Figure 3.10 shows the relation between the package area versus I/O for perimeter and area array packages. It is clear from Fig. 3.10 that for semiconductors with more than 100 I/Os, PGA and PAC packages have become increasingly attractive for packaging very-large-scale semiconductor ICs and ultra-large-scale semiconductor ICs. The scalable limit is determined only by fatigue issues of the solder connection or joint.
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