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SEMICONDUC TOR PACKAGING TECHNOLOGY
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MULTICHIP PACKAGES
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MCPs have emerged as a packaging option where performance is an issue or where interconnect area for connecting packaged ICs is at a premium. The performance issue is one of increasing semiconductor performance and the impact of the interconnect medium on the performance of the assembled die.The consequence of this is that the interconnects can no longer be considered to provide an instantaneous electrical connection. It can be shown that for copper conductors on polyimide at a clock frequency of 200 MHz, the maximum allowable length of interconnect is 170 mm, or about 6.8 in. As a reference point, the clock speed for the DEC ALPHA RISC microprocessor was 200 MHz or better in 1995. The clock speed of the Pentium III microprocessor is 500 MHz, and microprocessors with 1 GHz clock speeds are commercially available.
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Multichip Versus Single-Chip Packages MCPs for memory have found broad application in personal computer and laptop computer products. Multiple memory dies (packaged or unpackaged) are assembled on a rectangular interconnect (PCB or multilayer ceramic) with I/Os along one rectangular edge. Such a package is called a single inline package (SIP). The I/Os of the SIP can have DIP leads assembled on them for through-hole attachment onto PCB, or they can have lands on the package to mate with a suitable connector. For through-hole-mounted SIPs, the leads are usually on a 0.100-in pitch. Memory packaged in system-on-a-package or thin system-on-a-package or small-outline J-lead packages are assembled onto SIPs whose substrate is a PCB in appropriate multiples to offer enhanced memory capability. DCA or memory die is also possible. Figure 3.17 shows several SIP configurations. Figure 3.17(a) shows an early version of a SIP using a ceramic substrate and leadless ceramic chip carriers with soldered-on leads. Figure 3.17(b) shows a typical version of an SIP to mate with an SIP-type connector.
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FIGURE 3.17 SIP configurations.
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MCPs Using Printed Circuit Technology MCPs using PCB technology, but using leads on the substrate, are also being implemented to provide improved product functionality and board space savings. Figure 3.18 shows the concept of the lead-on-substrate MCP. The leads to the substrate can be fabricated integrally with the board during the PCB fabrication or can be soldered on using a suitable high-temperature solder.The lead-on-substrate MCPs can be postmolded or cover-coated with a suitable encapsulant.
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FIGURE 3.18
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LOS printed circuit MCP.
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The lead-on-substrate MCP could also be implemented using a cofired ceramic package with the leads brazed on and finished by cover coating with a suitable encapsulant or hermetic sealing of the assembled ICs. 7 of Ref. 7 gives a detailed discussion of the cofired multilayer ceramic package manufacturing processes.
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MCPs Using Organic Substrates The more prevalent form of MCPs uses a multilayer organic interconnect built on a substrate such as silicon, alumina ceramic, or metal composite.The dielectric films are patterned serially one on top of another to produce a multilayer interconnect. The dielectric of choice is polyimide with thin-film copper conductors. The technology for the interconnect in question uses processes and manufacturing equipment initially developed for semiconductor manufacture. This technology has a 1-mil line and space capability. The packages can have the cavity facing up (facing away from the PCB) or down (facing the PCB) if a heat sink is required for heat dissipation. Figure 3.19 shows wire-bonded die on a silicon substrate packaged in a premolded QFP and a ceramic QFP. A premolded QFP is a lead frame about which a plastic body has been molded and which contains a cavity for a die or a substrate. The method of interconnect from the silicon substrate to the package is wire-bonding. As shown in Fig. 3.15, bare die can be attached to the silicon substrate by die/wire-bonding, TAB bonding, or flip-chip bonding. As with the lead-on-substrate technology, the I/O format for the QFPs that house the multichip substrate follows the standards for QFP packages.
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