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FIGURE 27.17 Type I (six-layer HDI stack-up) shows one example of how to stack up an ML-PWB with HDI features.
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FIGURE 27.18 Type II six-layer stack-up having at its core a four-layer board with through holes, which later become buried.
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MULTILAYER MATERIALS AND PROCESSING
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FIGURE 27.19 Diagram showing how an HDI Type III (eight-layer HDI stack-up) might be produced employing conventional lamination techniques.
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Manufacturing capability becomes critical when targeting HDI features. The IPC has taken the responsibility of developing industry standards to assist in benchmarking and quantifying capability limits. Manufacturing features such as imaging, etching, hole formation, plating, and lamination registration are all strained and must be optimized. Other processes that are equally challenged are the end-product continuity testing to access the high-density features. 27.3.4.3.1 HDI Type I Stack-Up. Figure 27.17 shows one example of how to stack up an ML-PWB with HDI features. The economies of this design are obvious because it requires only one lamination cycle. The density push in this level of HDI focuses on imaging and microvia routing. By routing at a high circuit density, the surface area of the board is better utilized. The outerlayers are typically formed with a low height dielectric. When utilizing conventional lamination, this is usually a resin-coated foil or a microfoil bonded with a high-flow non-woven aramid prepreg. Special non-woven series of aramid fiber laminates have been developed to yield an equivalent dielectric thickness of 1.9 mil. Special handling is required for the microfoils, which are usually 9 to 12 mm thick. To facilitate handling, a sacrificial carrier foil is sometimes cohered to the microfoil externally for added stiffness. After lamination, one option is to process the microvias through laser drilling and conventional through-hole drilling. Sometimes a clad outer construction may be best, depending on the laser technology chosen. For example, infrared (IR) (CO2) laser ablation using an etched mask (small etched openings the size of the via) in the outer copper can be performed at primary print. This process helps reduce possible misregistration error. One metallization cycle is required to tie in all vias electrically. This reduces costs compared to sequential cycles. 27.3.4.3.2 HDI Type II Stack-Up. Density demands, when not met by the single lamination approach of Type I, must then address the use of sequential processing when employing standard ML-PWB techniques. The Type II stack-up shown in Fig. 27.18 has at its core a fourlayer board with through holes, which later become buried. 27.3.4.3.3 HDI Type III Stack-Up. The use of a Type III structure may be employed when routing densities are greatly pressed. At this point of complexity and above, alternative
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HDI approaches should be investigated because of the extra cost associated with performing repetitive cycles with conventional ML-PWB processes. Alternatives to lamination provide build-up of the dielectric and conductive layering through other means. These should be discussed with the manufacturer prior to selection. It is important to remember that the manufacturing method related to fabrication can have a great impact on the design rules chosen at CAD layout. Figure 27.19 represents how an HDI Type III might be produced employing conventional lamination techniques. Here, the core substrate is a four-layer ML-PWB detail similar to the Type II starting construction discussed earlier. Processing for the first pair of build-up layers follows the processing analogy of the Type II structure. Here, as in other foil laminated build-ups, the starting copper thickness should be kept to a minimum. Plating uniformity becomes critical when attempting to image/etch high-density features. After L2 and L7 have been defined, the final copper layer pair (L1 and L8) is laminated. At this final buildup, since no through holes are present, the flow of the resin-coated foil or prepreg should be sufficient to fill the microvias and flush the circuits. Once the additional layer is laminated, another level of microvias may be produced.
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Filled-Via Processing and Sequential Laminations The requirement to fill vias is driven most often by routing density. When high-density-area array components are utilized, the quantity of vias per square inch greatly increases in the local area under the device. Buried vias or blind vias are frequently the solutions to through-via starvation. Buried vias, unless otherwise prefilled, will fill with resin during final lamination. The volume of resin necessary to fill the buried vias is dependent on the diameter, length, and total quantity. Buried vias might straddle a single core, or might interconnect several cores and dielectric separations in a sub-lamination section. If there is insufficient resin in the prepreg to fill the buried vias, those vias can starve bonding resin from the local area where they are concentrated. To prevent the prepreg resin from entering the buried hole, the fabricator often is required to prefill the vias prior to a build-up lamination with a resin or paste formulation. Other design constructions require blind vias that are planar and within the land pattern at the surface mount attachment locations.These VIP structures free up real estate on the component attachment surfaces and provide enhanced signal integrity at high frequencies. Prefilling internal buried vias or blind VIPs with a hole-fill resin can provide a more robust interconnect structure, improved lamination integrity, and a planar surface in the case of the blind vias. 27.3.5.1 Fill Materials. Since the fill material is an additional fabrication material that becomes a part of the design construction, procurement documentation is required to specify a fill material type and thereby implement the via fill process. The selection and documentation of the fill material require the same consideration as the base laminate preference. This is especially critical when targeting a lead-free-compatible process. Currently, an industrybased material specification for via fill material does not exist. Therefore, specific fill-material brands may be named on the drawing, or some other form of user/supplier agreement must be established.The fabricator has preferences for the type of material used for via fill. Just as suppliers often have preferences for a specific solder mask brand, they also often prefer to use of a specific via fill material around which they have developed their principal processes. Supplier preferences can be driven by specific via fill material characteristics, such as accessibility, equipment compatibility, process supportability, plateability, and/or shelf/pot life. This may complicate source selection, or it might influence the use of a dedicated service center for the hole-fill process. The fabricator may not always know the reliability of its preferred material for a given via structure or end-use environment. Determining the properties of the various fill materials may be difficult for the user. Obtaining properties from the material suppliers data sheets may be possible for some properties, whereas others are more difficult to obtain; for example, many manufacturers data
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