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LAMINATION PROCESS CONTROL AND TROUBLESHOOTING
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A good lamination cycle produces a flat ML-PWB that is free of moisture or voids and has a fully cured substrate. All layers must be well registered. The ML-PWB must be free of warp and the thickness must be within the specification. Any controlled impedance layers must have the correct pressed dielectric separations above and below the signal layer. Each of these requirements puts special demands on the lamination process.To assist in setting control measures, the following process indicators (see Table 27.6) should be monitored with a Statistical Process Control (SPC) method.
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TABLE 27.6 Process Variables and Limits Process indicator Thickness control Heat rise /min. through melt Cure Post cure Registration Dielectric separation Specification limit Per engineering drawing or internal spec requirement Per resin system requirement Tg of resin system Dwell time/temp per resin system requirement Per engineering drawing or internal spec requirement Per engineering drawing Gauge type or method Over-arm micrometer Chart recorder TMA Chart recorder Appropriate coupons or x-ray inspection equipment Cross section
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Common Problems 27.6.1.1 Voids and Moisture. Substrate voids are a serious problem in many lamination processes. One source of these problems is moisture. B stage is very hygroscopic and must be stored in a low-humidity environment to preclude serious void problems. C-stage components also have a tendency to absorb water, and many fabricators use a bake to dry layers prior to lamination. However, for a fast innerlayer line with a good dryer in the oxide line, an innerlayer bake may not be necessary. Voids generally cluster in the low-pressure regions near the edge of the panel. This effect is minimized by the use of vacuum lamination. Increasing the lamination pressure can also reduce voids. However, the use of high pressures with high-flow materials can result in excessive flow, which leads to other substrate flaws such as resin starvation. 27.6.1.2 Blisters and Delamination. Blisters and delamination are also caused by trapped volatiles that collect in the low-pressure regions associated with print-through. If a board has wide copper borders on every layer, blisters are often found in the lower-pressure circuit areas adjacent to the borders. The best solution to this problem is to avoid areas of heavy copper adjacent to low-density circuit areas by replacing solid borders with a dot or stripe pattern. Also, the glass style and resin content of the prepreg should be matched to the weight of copper thickness adjacent to the prepreg. 27.6.1.3 Under Cure. The requirement of full cure is relatively easy to obtain if proper cure time and temperature are used. One measure of the cure level is Tg. Periodic measurements of Tg are an excellent check for material and process consistency. Another way to check cure is to make two consecutive measurements of Tg: If the epoxy is only partially cured, it will continue to cure during the first measurement and a higher Tg will be detected on the second measurement. A shift in Tg of more than 5 C is an indication of under cure. This measurement is typically performed on a TMA. Figure 27.39 shows an example of an epoxy TMA run; note that the second TMA run has a delta of 3 C. 27.5.1.4 Post-Lamination Bake. Many fabricators bake the ML-PWB at 150 C for up to four hours after lamination. One purpose of this baking is to ensure a complete cure.
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FIGURE 27.39 TMA analysis of epoxy with woven fiberglass. (Courtesy of Microtek Labs, Anaheim, CA.)
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MULTILAYER MATERIALS AND PROCESSING
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Although a bake will advance the cure, it is unnecessary if a proper lamination cycle is used (although polyimide is an exception; check the recommended processing guidelines). As discussed earlier, this can be verified by Tg measurements. However, additional baking beyond full cure degrades the material and reduces Tg. A second purpose of the bake is to reduce the warpage often seen in the outer boards of a stack-up. Although a post-lamination bake will flatten the boards, it is more of a repair than a root solution. If the panels are cured in the press in a way that ensures they go through Tg in an isothermal stress-free state, warpage should not occur. The warpage seen in the outer boards of a stack is generally a symptom of nonuniform cooling. The third purpose of a bake is to relax internal stress and improve registration. Internal stresses are a symptom of an overdetermined tooling system. If such a system is used, a bake may improve registration. If the more popular four-pin system is used, a bake is unnecessary. Always confirm the need of a post cure with the recommendations of the material supplier.
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27.6.2 Special Consideration for Non-Dicy, Non-Bromine, and LFAC Laminates For decades, the majority of PCBs have been built with epoxy resins, dicy-cured, and with bromine flame retardant.The industry has developed around this paradigm. Drills and drilling, chemistry, lamination, and circuit card assembly are all well understood with reference to standard FR-4. Although there are fabricators with processes developed to manufacture PCBs using laminates other than standard FR-4, this knowledgebase is not distributed industrywide. Especially problematic is the intersection of requirements for HF and/or LFAC with high thermal resistance and improved electrical characteristics, such as low attenuation in the material. Many laminators recognized that the heart of their product line would need to be revamped from the entry-level cost-conscious material all the way through to the highest performance material. This was a large undertaking, requiring many different trials to find the right ingredients, in the right combinations, with the desired properties, especially the response to the new elevated reflow temperatures. As is frequently the case, there are trade-offs. For instance, reducing CTE by increasing filler is desirable to a point; the increase of filler increases the dielectric constant and loss tangent properties of the material, making it less suitable for high-speed digital products. The line-up from the bottom to the top of the performance ladder, with and without bromine, capable of withstanding high-temperature reflow, isn t complete in all cases. These materials have not been in manufacturing and the field as long as the time-honed standard epoxy systems. Also, as they have been used, they have also been continuously refined which has caused processes to be continuously redefined. The major processes that need to be developed and optimized specifically for nonstandard FR-4 laminates are innerlayer adhesion promotion, lamination, drilling, and hole wall preparation. The fabricator must work closely with its laminate and chemistry providers to develop the specific process parameters that will work with their lamination equipment and chemistries. The major problems have been delamination (both adhesive and cohesive failures), voiding, and hole wall pull-away. Some of these quality problems can be discovered prior to shipment by cross-section analyses, but some do not manifest until after high-temperature reflow. Since laminators test laminates rather than finished PCBs, and fabrication and design features both effect the final product, a cautious fabricator will test completed PCB parts for quality and reliability, simulating the intended assembly soldering profile. Accordingly, submitting an actual final ML-PWB to multiple cycles through a production reflow oven with a lead-free soldering profile can be advantageous. After reflow exposure, the parts are visually inspected for blisters, then cross sections are taken at both high and low hole density areas to look for internal delamination or laminate cracks, voiding, and hole wall pull-away. Figures 27.40 through 27.43 show examples of these defects.
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