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Just as the name implies, MCM technology mounts multiple, unpackaged ICs (bare die), along with signal conditioning or support circuitry such as capacitors and resistors, to form a system, or a subsystem on a single substrate.1 In fact, in the late 1980s and early 1990s, MCMs were considered to be the ultimate interconnect and packaging solution, capable of meeting every challenge of the electronics industry. This technology placed ICs in close proximity to each other, thereby enhancing system performance by reducing interconnect delay.15 Size is often the primary driver for MCM-based systems. The typical multicomponent discrete assembly provides a silicon-to-board efficiency of <10 percent (actual total die area versus the total printed circuit board area). MCM technology can often increase the silicon-to-board efficiency to 35 or 40 percent with chip and wire assembly processes, and to 50 percent or higher with some of the higher-density processes.16 Thus, with reduced size and weight, MCMs offer a practical approach to reducing overall system size while providing enhanced performance due to a reduction in the interconnect distance between chips.1 Multichip modules typically use three to five times less board area than their equivalent discrete solution.16
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Since a multichip module is, by definition, a single substrate containing two or more ICs, it is unlikely that they are a thing of the past. Instead, they have been renamed from MCMs to MCPs, few chip packages (FCPs), or other similarly descriptive names. These packaging solutions usually contain from about two to six ICs that are packed onto an inexpensive laminate substrate. Although they are multichip modules, they may be called something else. Intel refers to its twochip package as a CSP, although in fact it is an MCP or MCM .17 Interestingly, some still believe that when time is an important consideration while reaching the market with a low-cost and reliable product, multichip solutions win. On the other hand, others believe that it s only a matter of time before SOCs take over completely and multichip packaging will not be necessary, and they view multichip solutions only as stopgaps.18 Nevertheless, regardless of their nomenclature, laminate based multifunctional packages are among the key package types in the industry.
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In general, an MCP is any package that contains more than one die. Low-cost solutions to multichip packaging are available for high-volume applications.11 Advanced electronic packaging technologies have historically been limited to applications in high-performance products such as supercomputers. Today, they are being moved into lower-cost products through the use of chip-on-board (COB), BGA, or land grid array (LGA) for second-level interconnect assembly, and surface-mount technology (SMT) mass production equipment. Prismark s December 2005 Report on Semiconductor and Packaging found that laminate packages constitute 47 percent of the overall packaging volumes followed by lead-frame packages at 39 percent. Improvement in the silicon efficiency of MCM designs can be accomplished by packaging ICs onto very-thin, compact, and lightweight microcarriers using BGA or LGA connections, such as those shown in Fig. 4.4. Because of the development of lower-cost materials (i.e., low-cost
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FIGURE 4.4 Photograph showing three different BGA packages and one LGA package: in the top-left, 1,600-pin FCBGA (1.0 mm pitch, ceramic substrate); in the top-right, 1,140-pin FC-LGA (1.0 mm pitch, build-up substrate); in the bottom-left, 768-pin TAB-BGA (1.0 mm pitch); and in the bottom-right, 672-pin EBGA (1.27 mm pitch). (Photograph provided courtesy of Fujitsu Microelectronics, Inc.)
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photosensitive materials), large-area processing (as practiced in the fabrication of displays), large-area lithography, and low-cost metallization processes as practiced in printed wiring board (PWB) fabrication, economically viable multichip packaging is realistic.19
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Few Chip Packaging (FCP) An increasing number of companies are embracing FCP for technical and business reasons. Although these FCPs are virtually indistinguishable from their single-chip packages, they are a radical departure from the MCMs of the early 1990s. Instead of 10 to 20 die, today s FCPs typically contain two to five die mounted on a laminate substrate in a BGA package. This rebirth can be attributed, at least in part, to improved bare die testing and handling, along with the availability of low-cost, high-performance laminate substrates. Furthermore, there is a growing trend to use FCP as an alternative to SOC, resulting in a system-in-a-package (SIP). This approach is also referred to as SOP.
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Chip-Scale Packaging (CSP) CSP was introduced in Japan in the early 1990s and in the United States soon thereafter as a less expensive alternative to MCMs.20 According to IPC/JEDEC J-STD-012 definition, CSP is a single-die, direct-surface mountable package with an area of no more than 1.2 times the original die area. CSPs come in many forms wire-bonded, flip-chip, leaded, and BGA. A typical wire-bonded CSP packaging process (Fig. 4.5) starts with the attachment of the die on
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