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FIGURE 4.5 Schematic of a wire-bonded CSP.
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an interposer using an epoxy. Wire-bonding is then performed from the I/O pads of the die to the interposer. These wirebonds must be as low and as close to the die as possible to achieve the minimized package size. A plastic transfer molding process is used to encapsulate the die. Finally, solder balls are formed on the bottom of the interposer. In flip-chip CSPs, the solderbumped die is bonded onto the interposer as shown in Fig. 4.6. The area-array version of CSPs, also known as fine-pitch ball grid assemblies (FPBGAs), is now widely used in many portable and telecommunication products.
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FIGURE 4.6 Schematic of a flip-chip CSP.
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FIGURE 4.7 Photograph of several chip-size packages. On the left are logic CSPs: Row 1: 352-pin TAB-BGA (0.80 mm pitch) Row 2: 288-pin FBGA (0.5 mm pitch) Row 3: 48-pin BCC (0.5 mm pitch) Row 4: 16-pin BCC (0.65 mm pitch) On the right are memory CSPs: Row 1: 60-pin mBGA (0.8 mm pitch) Row 2: 46-pin SON (0.5 mm pitch) Row 3: 48-pin FBGA (0.8 mm pitch) Row 4: 16 M bit flash memory chip (Photograph provided courtesy of Fujitsu Microelectronics, Inc.)
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CSPs have smaller size, lesser weight, and improved electrical performance. CSPs offer the same space and material savings and short signal paths as direct chip attach (DCA) methods such as COB and flip-chip-on-board (FCOB) offer. The advantages of using a chip-scale package over DCA are easier handling, more protection for the chip, and simpler board assembly. Figure 4.7 shows a selection of commercially available CSPs. CSPs are somewhat limited to use in moderate I/O ICs.20
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Wafer-Level Packaging (WLP) Wafer-level package is defined as an IC package completely fabricated at the wafer level and assembled with standard SMT. Alternatively, a wafer-level package can be defined as the package in which the die and package are fabricated and tested on the wafer prior to singulation. Significant reductions in cost and device form factor can be achieved with WLP, while at the same time increasing the electrical performance. Wafer-level packaging was first investigated by Sandia National Laboratories and Fujitsu in the mid-1990s. Since then, WLP technology has been applied to flash and dynamic random access memory (DRAM) devices. However, widespread market adoption of WLPs has yet to occur. A WLP is not the
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optimal package for high I/O devices because of the limitations of the SMT assembly process and the wiring constraints of the printed circuit board (PCB) to which it is mounted. WLPs are typically used in devices that are small, with 2 to 36 bumps, such as in power metal-oxide semiconductor field effect transistors (MOSFETs), electronically erasable read-only memory (EEPROM), small logic devices, and transient voltage suppressors. Cellular phone market consumes more than 90 percent of all WLPs produced today. This is because WLPs enable the small form factor and increased functions desired in modern cellular phones. However, there are indications that higher-end DDR2 and DDR3 DRAM devices will be able to take advantage of the benefits offered by WLPs. Several factors must be addressed in adopting WLPs. These factors include I/O density, reliability, burn-in, assembly processes, and cost. It is important to remember that a WLP is not the ultimate package for certain devices. The benefits of wafer-level packaging can be summarized as follows:
Smallest IC package size, as it is truly CSP Lowest cost per I/O because the interconnections are all done at the wafer level in one set of parallel steps Lowest cost of electrical testing, as this is done at the wafer level Lowest burn-in cost, as burn-in is done at the wafer level Elimination of underfilling with organic materials around the solder joint Enhancement of electrical performance because of the short interconnections
According to the latest ITRS roadmap, the pitch of area-array packages is expected to decrease to 100 mm by 2009. Simultaneously, the electrical performance of these interconnections needs to be improved to support data rates in excess of 10 Gbps, while guaranteeing thermomechanical reliability and lowering the cost. These requirements are thus challenging, requiring innovative interconnection designs and technologies. To meet these challenges, nano wafer-level packaging that uses nano materials and structures to bring about unprecedented advances in electrical, mechanical, and thermal properties in the chip-to-package interconnections is being investigated.21, 22
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