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Three-Dimensional (3-D) Packaging
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Another type of multichip packaging gaining wider acceptance is stacked die packaging.23, At the present time, most packaging of this type is in the form of stacked memory in CSPs, and the stacking is done only to save space. However, it is a growing trend that can be applied to any electronic system where volume density is of concern. Stacked die packaging is illustrated in the top view of Fig. 4.8, while the bottom view shows how packaged devices can be stacked. The advantages of stacked die packaging are further enhanced by using thinned die. Thinning die has the potential of enhancing first-level interconnect reliability while minimizing the increase in vertical profile. A silicon die with a thickness <100 mm is quite flexible and can relieve stresses induced by packaging and coefficient of thermal expansion (CTE) mismatch.26 The latest in IC packaging is a stacked ball grid array (SDBGA) package for the communication market. It is used to stack various ICs in one package with the resulting savings in real estate on the motherboard and manufacturing cost. Compared to conventional packages, an area savings of up to 70 percent can be realized. Popular SDBGA sizes range from 8 mm 8 mm to 14 mm 14 mm and a pin count between 80 and 140. The total package height is typically about 1.4 mm.
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FIGURE 4.8 Drawings illustrating 3-D packaging: at the top, die (or chip) stack packaging; at the bottom, package stacking.
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The end application and the electrical, thermal, and reliability performance demands it presents on the package often dictate the choice of assembly materials, assembly process, and package test technologies. For packages that involve multiple die or components, the need for known good die cannot be overemphasized. Applications such as cell-phones, where the available space has a premium but which demands an increasing functionality, may require enabling technologies such as wafer thinning along with stacked die or stacked package. However, in view of the relatively small product lifetime, the reliability requirements may be somewhat more forgiving than those for a server application, wherein the long product lifetime, large body size, high electrical signal speeds, and high power dissipation pose a different set of challenges. This section will review some of the key enabling technologies required across different application spaces and will also discuss the resulting impact of lead-free requirements.
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Known Good Die (KGD) When an electronic system is fabricated or an electronic component is assembled, KGD considerations play a very important role in minimizing waste, optimizing the material, and
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infrastructural resources, and keeping the costs low.27, 28 Packaging and test combined, especially that for high-performance devices, form a higher fraction of the total device cost today than it did a few years ago. Consequently, it makes even more sense to weed out the known reject die and not let it into the assembly process. By doing so, the manufacturer can control the overall cost of packaging while simultaneously using the assembly equipment time only for known good subcomponents. This requirement directly translates into a need for developing adequate test and probe technologies that are suitable for flip-chip as well as wire-bond devices. Shrinking pad pitches and narrowing geometries require the development of advanced wafer probe technologies. 4.6.2 Chip Thinning As noted in a previous section, one approach to increasing the functional density of an electronic system is to stack ICs vertically. Reducing the thickness of the chips allows for more chips to be stacked within a package, thereby substantially increasing the functional density. In addition to increasing the functionality per unit area of substrate (module), thinning chips also improves their thermal performance, results in a more mechanically reliable device, allows for flexibility so they can conform to a curved surface, and relieves stress induced on a chip due to packaging26, 29 Thinning chips can result also in an improved electrical performance in view of the reduced signal path across two or more chips. However, this is not necessarily always the case, as cross-talk and interference across the chips can also increase due to the reduced distance, thereby potentially degrading the electrical performance. Decoupling capacitors may be needed for adequate isolation; however, a more detailed electrical analysis is beyond the scope of this chapter. Four techniques that are primarily used for wafer thinning are mechanical grinding, chemical mechanical polishing (CMP), atmospheric downstream plasma (ADP, sometimes used with wet etching), and dry chemical etching (DCE). Factors to be considered when selecting the appropriate thinning technique include the throughput of the time taken to thin a wafer, quality, and defect density in the resulting thinned surface, and cost. Due to its high material removal rate, mechanical grinding continues to be the most popular method for wafer thinning. However, this technique also introduces to the thinned surface a significant amount of mechanical damage that needs to be removed. This is achieved by fine grinding or through CMP, which relies on chemically assisted mechanical polishing of the wafer surface. CMP can deliver very flat and defect-free wafer surface, however, the material removal rate is small of the order of a few micrometers per minute. Thicknesses routinely achieved vary from 50 to 100 mm, FIGURE 4.9 Photograph of a silicon wafer although thicknesses as small as 15 to 25 mm (silicon is that has been thinned to approximately 50mm flexible in this thickness range) have been demon- by plasma etching. Warpage was caused by the wafer thinning process. (Photograph provided strated.30 Figure 4.9 is a photograph of a silicon wafer courtesy of Materials and Manufacturing that has been thinned to approximately 50 mm using a Research Laboratories, University of Arkansas, Fayetteville AR.) plasma process that causes bending of the wafer.
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Lead-Free Chip Attach Processing Packaged devices require a larger amount of real estate as compared to the die due to the requirement for a substrate (or chip carrier ).31 Substrates provide electrical connections from the die bond pads to the external world. Bare die attachment eliminates the need for a
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