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substrate, thereby saving valuable module space and reducing interconnect distance, but such system configuration can increase the risk of reliability performance of the system. Direct die attachment can be accomplished by conventional die attach/wire bonding, tape-automated bonding (TAB), and flip-chip processes. Lead-free requirements impose the following additional requirements:
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Use of suitable lead-free materials in the assembly bill-of-materials Compatibility of these materials with lead-free processing temperatures
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Performance of the package moisture sensitivity level (MSL) can be impaired by the higher temperature compatibility arising from lead-free requirements. 4.6.3.1 Wire Bond. For most part, transition to lead-free of a wirebond package on a component level is relatively straightforward. Through the use of gold wires, the first level interconnect is already lead-free. Further, most of the metal lead-frame-based packages are lead-free-compliant as long as the mold compound or the die-attach materials are free of lead or similar components and are able to withstand the higher temperatures seen by the package during component reflow. BGA-based wirebond packages, on the other hand, additionally need use of lead-free BGA balls on the package to make it compatible with leadfree requirements. 4.6.3.2 Tape-Automated Bonding (TAB). TAB is rather expensive because it requires a custom tape for each different IC and its construction requires a significant amount of processing. Furthermore, the assembly process is equipment-intensive because of testing of the IC while it is mounted on the tape, excising the IC from the tape and shaping (forming) its leads prior to mounting it onto a substrate, requiring a custom die for gang bonding. However, it is attractive because it provides the opportunity to perform burn-in and die testing prior to final assembly. The TAB process is schematically illustrated in Fig. 4.10. TAB packages are usually naturally lead-free at the component level. Assembly to the application board does require lead-free solder along with a requirement for the package to be able to withstand the high temperatures associated with lead-free processing. 4.6.3.3 Flip-Chip Bonding. The flip-chip assembly technique is one of the important techniques of die attach to either the carrier (substrate) or directly to the board usually employing either solder bumps or z-axis conductive polymers. Another common mode of attaching silicon dice in the flip-chip configuration is stud bumping, where a gold wire is used in a similar fashion as in wirebonding, but the wire is truncated after establishing contact to the die pads. The resultant stud is then flattened using a coining process. The original flip-chip assembly, pioneered by IBM, eliminates all the packaging area that is not occupied by the die itself, generally resulting in the smallest footprint and the lowest profile. However, wirebonded devices can be back-ground to reduce the overall package thickness. It is not trivial to perform a similar back-grinding operation on flip-chip devices for two reasons. First, the bumping process prefers to use full thickness wafers due to breakage concerns, and second, it is extremely difficult to back-grind bumped wafers. In general, flip-chip assemblies can use either grid arrays or peripheral pads for I/O connection at pitches between 0.1 and 0.65 mm, but are limited mostly by routing constraints through substrate manufacturing capabilities. Consequently, most flip-chip devices in production today use a solder bump area-array pitch in the range of about 0.15 0.25 mm. Of all the techniques available, flip-chip assembly offers the highest packaging density and there is increased use of flip-chip attachment. Consequently, many bumping contractors also offer redistribution services. Although redistribution is done on the chip (actually on the wafer), it is considered a packaging operation. Additional requirements presented by the need for lead-free, RoHS-compliant, green packages call for lead-free solder bumps. Devices that use gold stud bumps previously referenced are
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