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FIGURE 4.10 Schematic of the TAB process.
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already lead-free; however, stud bumping is typically limited to a smaller die and those with a small number of I/O count requirements (note that I/O here refers to the total number of connections required across the die and the carrier/substrate). Furthermore, the stud-bumpbased lead-free solution has its challenges due to the serial nature of the stud-bumping and die-attach processes. Consequently, a lot of effort continues to go into the development of lead-free solder-based wafer bumping. Lead-free wafer bumping is discussed in more detail in the next section.
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Using Barcode creator for Software Control to generate, create Code 128B image in Software applications. Wafer Bumping. Wafer bumping is a wafer-level packaging technology that uses solder bumps to form interconnects between the integrated circuit (IC or chip) and the actual package. To create a solderable site with an electromigration barrier, the manufacturer usually first deposits an under-bump metallurgy (UBM) of electroless nickel and gold directly onto the I/O pad of the IC. Other typical UBM consists of a 20 50 nm of evaporated chromium acting as contact and adhesion layer, a diffusion barrier of 100 200 nm of Cr:Cu, a conductive layer of 0.4 0.6 mm of copper, and finally an optional oxide protector of about 100 nm of gold.This is followed by the placement of solder either by evaporation, electroplating, or screen printing onto each I/O site and a thermal reflow to form a solder ball as shown in Fig. 4.11.
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Under bump metallurgy (UBM)
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Solder bump Device passivation
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Final metal pad
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FIGURE 4.11 Schematic of a solder bump and underlying metallurgy.
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Flip-chip ball grid array (FCBGA) is a package type that uses solder bumping to yield areaarray interconnection.Area-array interconnection ensures signal and power/ground integrity far more superior to conventional peripheral wire-bonding interconnection due to elimination of wirebond inductance and a lower electrical resistance. Solder bumping enables the realization of CSPs. CSPs are well accepted in handheld consumer products such as cellular phones and PDAs, since the package size is of vital importance. However, the ultimate package is a true chip size package, the wafer-level CSPs (WL-CSP). WL-CSP is predicted to enjoy the highest continuous aggregated growth rate (CAGR) of more than 20 percent since it enables high-performance microprocessor chip (MPU), application-specific integrated circuit (ASIC), and memory devices for the high-end computing and networking markets. Bumped die for FCOB assembly is common in electronic manufacturing due to the saving in the printed circuit board real estate. There are three primary wafer-bumping processes for solder placement: screen printing, electroplating, and evaporation. All these processes have been used in production, but bump pitch, I/O count, start-up cost, and production volume are critical criteria that dictate which process is best for a particular solder placement. Evaporation of solder requires substantial investment in capital equipment since it is performed in a high-vacuum environment. Electroplating of solder yields a finer solder bump pitch, but it is primarily limited to solders with binary alloys such as SnAg and SnCu. Screen printing of solder is the most cost-efficient for solder bump pitch greater than 120 mm.32 Solder bumps must undergo a reflow process to create the solder bump structure shown in Fig. 4.11 as a result of its surface tension. Since the composition of the solder may be highlead, eutectic, or lead-free, the equipment and processes must be capable of handling a wide range of temperature profile variations while maintaining a tight thermal uniformity within each process profile. A typical reflow process undergoes five transitions: pre-heat, flux activation, soak, reflow, and cooldown.The purpose of the pre-heat is to evaporate solvents from the solder paste. A slow thermal ramp-up rate prevents damage due to thermal shock. The time and temperature to evaporate the solvents depends on the solder paste that is applied. As the temperature is ramped up, the flux reacts with the oxide and contaminants on the surfaces to be joined. The time and temperature should be long enough to allow the flux to clean these surfaces fully, but not so long that the flux may be exhausted before soldering takes place. The soak temperature should be approximately 20 40 C below the peak reflow temperature.
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