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Time and temperature depend on the mass and solder materials. During reflow, the assembly is briefly brought to the temperature sufficient to reflow the solder. After reflow, a gradual cooling should be used to prevent thermal shock. Gradual cooling produces a finer grain structure and fatigue-resistant solder joint. During reflow process, care must be exercised to prevent the formation of oxides that degrade subsequent processes. A nitrogen-with-flux or hydrogen-flux-free reflow process has been used to control oxide formation. There is a trend in the industry toward smaller area-array packages with lead-free bump sizes in the range of 10 15 mm. Metal bumps, including gold, copper, and nickel, are lead-free wafer bumping.33 In addition, gold and copper have a greater mechanical shear strength compared to lead solders. This helps to relieve residual stresses caused by the mismatch of the CTE between the chip and printed-circuit board materials, and hence strengthens the bump connections.34 Gold stud bumps are formed by a modified wire bonder that uses thermosonic energy (150 200 C) to first attach a gold bondwire to the die bond pads and then shear the top of the gold wire without leaving a tail.35 To achieve a uniform bump height, the gold studs may be flattened or coined by pressing any remaining wire tail to the ball or shearing it off. This yields a planar, flat-top gold bump that does not require any coining in a single-step process. Copper is another candidate material for wafer bumping. Compared to gold, copper costs less but has a good electrical and heat-dissipating performance due to its low electrical resistivity and high thermal conductivity. Copper studs can be created by bonding a copper bondwire directly onto the aluminum bonding pads on a wafer using a thermosonic bumping machine. However, the ultrasonic power and bonding force required for copper studs are generally higher than those for the gold studs due to the hardness of copper. Also, a reducing gas, usually 5 percent hydrogen in nitrogen, is blown over the end of the copper wire during formation of the ball to prevent oxidation of copper. Copper bumping has many advantages over solder and gold bumping in terms of increased electrical and mechanical performance and reduction of material cost; however, it is relatively new to the flip-chip industry. 4.6.3.5 Chip-on-Board (COB). In COB assembly, a back of a bare (unpackaged) IC is attached directly onto a PWB, wire-bonded, and then encapsulated with a polymer. The die bondpad pitch is generally in the range of about 0.175 0.25 mm and IC placement must be very accurate. For many applications requiring miniaturization, and especially those where space is limited, COB assembly can be the most cost-effective packaging option. It is a mature technology and offers high packaging density, low packaging cost, and fast signal speed because the dies are wire-bonded directly onto a board.36 The photograph in Fig. 4.12 shows details of a COB-mounted power diode. Usually, as a final step, a glob top is deposited onto the chip to serve as passivation and protection.
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FIGURE 4.12 Photograph of chip-on-board. (A COB assembly).
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4.6.3.6 Passive Devices: Surface-Mount Components. Since the invention of the IC, almost continuous progress has been made in creating a given functionality in a smaller area. Unfortunately, surface mount (SM), discrete passive (DP) component size, which has seen continuing size reductions from 0805 components (80 mils 50 mil or 2 mm 1.25 mm) to 0201 components (20 mil 10 mil or 0.5 mm 0.25 mm) with preliminary work being done on 0105 components (10 mil 5 mil or 0.25 mm 0.125 mm), has not shrunk accordingly. Furthermore, increasing numbers of DPs are required in newer electronic systems. Consequently, DPs can occupy significant substrate area. In fact, system substrates are now dominated by
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