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chip capacitors tend to be more fragile than the alumina body of a chip resistor. The built-up layer structure of MLTF capacitors causes them to be particularly susceptible to both mechanical and thermal shock. Chip capacitors use similar metal layers to build up the terminations that are soldered to the circuit board pad as were described previously for resistors. Chip inductors are of two types as well. Coil inductors are comprised of a fine Cu wire wound around the alumina body. The body size and number of windings determine the part inductance. The second type is the thin-film inductor. The winding is fabricated from a patterned thin film, which is deposited upon a piece of alumina. (Although the latter are considerably easier to fabricate, they have a limited range of inductance values.) As much as 40 percent of passive components on a surface-mount product are chip capacitors. The miniaturization of these devices is critical for reducing the size and weight of electronic products. For handheld electronics (such as cell-phones, PDAs, and pagers), common capacitor sizes are from 0603 down to 0402 and 0201. Some diodes and all active devices come in a wide variety of peripheral lead and area-array packages.The diodes and transistors are typically used in small-outline (SO) packages; they are the small-outline diode (SOD) and small-outline transistor (SOT) packages.The package body is a plastic overmolding compound. There are two leads for the SOD and three for the SOT. The leads are very robust, have a gull-wing shape, and are formed from Cu or an Fe-based alloy. Larger active devices require more I/Os. These devices use the small-outline integrated circuit (SOIC) package with gull-wing leads protruding from the two sides of the long dimension. The gull-wing leads are very robust with a pitch of 1.27 mm (50 mil) or 0.635 mm (20 mil). Pitch is the distance between the centerlines of two neighboring leads. A further increase in the number of I/Os was realized by placing leads around all four sides of the package; the leads can have the gull-wing geometry or have the J-lead geometry. The J-configuration reduces the bond pad area by bending the lead inward, under the package. Like the gull-wing, the J-lead geometries are robust at 1.27 mm (50 mil) and 0.635 mm (20 mil) pitches. Pitches below 0.635 mm, beginning with 0.5 mm and 0.4 mm pitches, are called fine-pitch (package) technology. The smaller leads are considerably more fragile, causing them to be more susceptible to damage during handling and pick-and-place activities. Also, the fine-pitch packages have a more stringent coplanarity requirement for the leads. Coplanarity specifies the degree to which the lead bottoms must be at the same level around the periphery of the package. A non-coplanar lead one that is lifted high is more likely to generate an open because of the reduced amount of solder used for these smaller I/Os. A lead that is too low will be damaged during package placement and also displace the solder paste deposit, causing a defective joint or short circuit to a neighboring lead after the assembly step. A second type of peripheral I/O package is the leadless ceramic chip carrier (LCCC). This package is made of ceramic material; the I/Os are castellations on all four sides of the package. Solderability of the castellations is obtained by a Ni finish over which is deposited an Au layer. The Ni and Au layers extend down the castellation and under the frame to form a pad. This package can be used only on so-called matched or low-expansion substrates, that is, circuit board substrates with a thermal expansion coefficient that matches that of the ceramic package. Otherwise, the solder joints are quickly degraded by thermal mechanical fatigue (TMF) when exposed to even modest cyclic temperature environments. Area-array packages include the BGA, CSP, the land grid array (LGA), DCA/FC, and the ceramic column grid array (CCGA). The common characteristic of these packages is that the solder joint is made to an array of solderable pads on the bottom side of the package rather than to peripheral leads or castellations.The difference between a BGA package and a CSP package is that the latter is stipulated to have molding compound dimensions that are less than 1.2 times the corresponding die dimension. There are no specified limits on a BGA package size. The typical pitch size is 1.27 mm and 1.0 mm for BGA and CSP packages. Here, the pitch is the distance between the center points of any two balls or lands. Therefore, alignment requirements are not very stringent for these area-array packages. Also, there is a sufficient quantity of solder to allow self-alignment between the package and circuit board pads by the surface tension of the molten solder. However, as ball counts reach several thousands, reduced ball
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