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ACCEPTABILITY AND QUALITY OF FABRICATED BOARDS
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Pit or dish-down This is a depression in the conductive layer that does not penetrate entirely to the base material but does reduce the cross-sectional area of the conductor. These imperfections are almost impossible to detect as they rarely give visual cues to the inspector. Scratch This is a slight surface mark or cut that may or may not go all the way through to the base material. Void or Pinhole This is the absence of conductive material in a localized area going all the way to the base material.
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51.11.1.3.1 Conductor Width. The conductor width is the observable width of a conductor at any point chosen at random on the PCB, normally viewed from vertically above unless otherwise specified. The conductor width affects the electrical characteristics of the conductor. A decrease in conductor width decreases current-carrying capacity and increases electrical resistance. Although the conductor width definition is very basic, there are two different interpretations as to where on the conductor the measurement is performed. The minimum conductor width (MCW) is measured at the minimum observed width of the conductor, and the overall conductor width (OCW) is measured at the observable width. Plating outgrowth of the top of the conductor during pattern plating can prevent the minimum width from being seen unless cross-sectioning is performed. The OCW is nondestructive and easily measured. The difference between the MCW and the OCW (see Fig. 51.6), which is measured from vertically above, can have an effect on the current-carrying capacity, inductance, and impedance of the circuit. IPC-6012, Qualification and Performance Specification for Rigid Printed Boards, addresses conductor width requirements and allows added width reductions for edge roughness, nicks, pinholes, and scratches of 30 percent (Class 1) and 20 percent (Classes 2 and 3) from the minimum specified on the procurement documentation. The document states that this reduction also applies to the MCW reflected on the procurement documentation, and this allowance should be carefully considered against design needs.
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FIGURE 51.6 Overall conductor width (OCW) measurement W. (Courtesy of IPC.)
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51.11.1.3.2 Conductor Spacing. Conductor spacing is the distance between adjacent edges (not centerlines) of isolated conductive patterns or features. The spacing between conductors and/or lands is designed to allow sufficient insulation between circuits. A reduction in the spacing can cause electrical leakage or affect the capacitance of the circuit. The crosssectional width of conductors is usually nonuniform. Therefore, the spacing measurement is taken at the closest point between the isolated conductors and/or external annular ring (the portion of conductive material completely surrounding a hole). 51.11.1.3.3 External Annular Ring. The portion of conductive material completely surrounding a hole is called the annular ring (see Fig. 51.7). The primary purpose of the annular ring is that of a flange surrounding the hole; it provides an area for the attachment of electronic component leads or wires and acts as an anchor for the circuit. The minimum annular ring dimension needs to be defined by the PCB user and will differ based upon the function of the
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holes and whether they are plated or not. Annular ring dimensions that are less than those specified can interfere with attachment of the component, and a pad breakout (zero annular ring) condition associated with the area where the circuit enters the pad can reduce the current-carrying capacity of the circuit. After verifying the dimensions of the PCB and then verifying that the minimum widths of the annular rings on all other lands are within the procurement documentation requirements, the pattern is found to be in registration with the drilled hole location. Front-to-back pattern registration can also be inspected in this manner. 51.11.1.3.4 Plating Adhesion. A common method of inspecting for plating adhesion is the tape adhesion test, which is described in detail in the IPC test method IPC-TM-650, 2.4.1. The basic test method is performed by adhering tape of known properties onto the plating, rapidly removing the tape, then FIGURE 51.7 Minimum external annular ring (includes plating). (Courtesy of IPC.) inspecting the tape for removed plating on the tape adhesive. 51.11.1.3.5 Peel Strength. Peel strength is the force per unit width required to peel the conductor or foil from the base material. It is usually associated with the acceptance testing of copper-clad base material upon receipt, but it is sometimes used to test the adhesion of the conductors to the finished PCB. Peel strength tests of conductors are usually performed after the specimens have been dip or reflow soldered. Peel strength tests of conductors are a good method of ensuring that the conductor-to-base material adhesion is sufficient to withstand assembly and rework operations. 51.11.1.4 Hole Characteristics. PTHs provide circuit interconnection from the surface of the PCB to internal layers and to circuitry on the opposite side. For this reason, much attention is correctly focused on the acceptability and quality of these holes. Nonconformance in the PTHs is a serious concern. 51.11.1.4.1 Roughness and Nodulation. Roughness is an irregularity in the side wall of a hole; nodulation is a small knot or an irregular lump found in or on the plating. Although roughness and nodulation are not desirable, they are allowable in small amounts. Roughness and nodulation create one or more of the following nonconforming conditions:
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Reduced hole diameter Impaired lead insertion Impaired solder flow through the hole Voids in solder fillet 51.11.1.4.2 Voids in the Plating and Finished Coating. A void is the absence of material where it is intended to be. Copper-plating voids are evaluated again during microsectional analysis, but this sampling is very small and this attribute should be thoroughly evaluated during visual inspection of the PCB. When visually evaluating voids in the PTH copper, no more than 5 percent of the holes on the PCB should exhibit evidence of voids. In holes that have voids (see Fig. 51.8), there should be no more than one void that is less than 5 percent of the hole length. Voids in the finish coating of the PCB (see Fig. 51.9) that do not extend to the copper plating are allowed in larger quantities than voids in the copper plating. There should again be surface finish voids in no more than 5 percent of the PCB holes, and these holes should have no more than three voids that are each less than 5 percent of the hole length.
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