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Copyright 2008 by The McGraw-Hill Companies. Click here for terms of use.
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structured testability. Before jumping into the DFT discussion, however, some definitions are crucial.
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54.2 DEFINITIONS
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These definitions are fully discussed in Chap. 55 and are repeated here in an abbreviated form for reference. 1. 2. 3. 4. A defect is an unacceptable deviation from a norm. A fault is a physical manifestation of a defect. A fault syndrome is a collection of measured deviations from an expected good outcome. A fault is detected when an operation with an expected outcome is conducted and this outcome is not observed. 5. A fault is isolated when an operation with an expected good outcome and one or more failing syndromes is conducted and the outcome matches a member of the set of failing syndromes. 6. A test is one or more experiments that are specifically constructed to detect (and possibly isolate) failures. A detection test has an expected good outcome. An isolation test has an enumeration of possible fault syndromes indexed to specific failures. The technology of testing, as covered in Chap. 55, is highly influenced either positively or negatively by the design of boards being tested. If the preceding definitions are not clear, then the discussion of loaded board testing should be digested first.
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54.3 AD HOC DESIGN FOR TESTABILITY
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Ad hoc design for testability consists of a set of simple design rules of the form Do this, don t do that, where this and that are often not motivated with reasons. For example, when designing a board with ICs that have preset or clear pins, a rule might read as follows: Tie unused preset and clear pins off through a 100- resistor to a power rail; do not tie them directly. The first-level reason for this is that a test engineer might want to access the preset/clear functions during testing, even though the designer did not use these functions. If these pins are tied through a resistor, a test engineer may still be able to manipulate them by applying a tester resource to them that can drive a signal in spite of the resistor. If these pins are tied directly to a power rail, the test engineer will never have that option. What might the difference be Well, in a deeply sequential circuit, controlling the preset and clear functions might make the difference between a test that runs in milliseconds versus hours. Clearly, hours of testing (per board) are impractical, so the bottom line may be the difference between a thorough test and one that lacks significant fault coverage, affecting quality. The real reason for the various ad hoc DFT rules is that, to effectively and economically test a circuit, one must be able to control and observe the circuit s behavior. Most rules are related to controllability and/or observability of the circuit. The rule just cited is a controllability rule. Observability rules typically suggest ways one might be able to monitor signals that are deeply embedded in combinatorial circuitry, or that are activated only rarely by complex sequential events.
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Ad hoc DFT is essentially the only way many products can have improved testability when those products are constructed with off-the-shelf merchant parts. Large, vertically integrated companies have the advantage of being able to customize testability into the heart of a design, including the very ICs themselves. Application-specific ICs (ASICs) allow more of this as well.
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54.3.1 Physical Access Testing is performed once the board to be tested is connected by some adaptor mechanism to the test system. This may be accomplished via the edge connector(s) of the board, where the tester is given the same access that the board gets in its end application. But far more common is bed-of-nails in-circuit test access, where the board to be tested is physically mounted on a platen and depressed into a field of precisely positioned spring-loaded probes ( nails ) that contact hundreds or perhaps thousands of internal board nodes. (See Sec. 55.4.2 in Chap. 55.) This can be a challenging mechanical proposition to implement, particularly when high-volume, reliable manufacturing is the goal. Board designers must consider physical attributes of their boards early in the design process. They have a size target and then often find that there are density issues that may require fineline geometries and two-sided component mounting to solve. The fact that in-circuit bed-ofnails access may be needed for testing should also be considered very early. See Ref. 2 for an excellent discussion of how test target pads need to be provided, and how artifacts of the board layout (particularly vias) may be used to satisfy some of these needs. However, due to the density revolution, full nodal access, which has been the holy grail of in-circuit testing, is often impractical. This leads to the question of what access is most important when full access is impossible. The answer to this question comes from the domain of circuit design.
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54.3.2 Logical Access Sometimes it is impractical to gain physical access to all nodes of a circuit. For example, Fig. 54.1(a) shows an IC containing a large amount of complex logic, much of it deeply buried and effectively inaccessible from the I/O pins. Figure 54.1(b) shows the same IC with two additional gates added. The first is an exclusive OR gate that collects three buried signals,
FIGURE 54.1 (a) An integrated circuit with deeply buried logic. (b) Same IC with controllability and observability logic added.
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