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adds them together,* and brings the result to a spare I/O pin. This makes the states of those three signals much more observable. The second gate is an OR gate that allows us to insert a 1 from a spare input pin into a deeply buried portion of the circuit. The assumption here is that the modified signal rarely reaches the 1 state in normal operation, so this extra controllability enhances our ability to manipulate the circuit for test purposes.Adding these extra gates can make it much easier to control and observe the performance of the IC. However, the downside is that we consumed a small amount of silicon area for the two gates, and, perhaps more importantly, we utilized two additional I/O pins. For many ICs, the extra cost of the pins could be a negative factor. The choice of the optimal places to insert controllability and observability is not always clear, but rather is a trade-off of extra circuitry and pins vs. the difficulties that may be experienced in creating tests. There may be additional concerns as well with respect to circuit performance. For example, adding the controlling OR gate in Fig. 54.1 could add some signal propagation delay into the affected pathway, with detrimental results on system performance. When ad hoc circuit modifications are made for the sake of testability, it is likely that seat-of-the-pants decisions will be made rather than critical analysis. One person s decisions might be remarkably different than another s, with resulting great variability in testability improvements.
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Structured DFT was born inside companies that had vertical control over their designs, from custom ICs through systems. They also were well aware of their testing costs and realized that initial design decisions had a large impact on these downstream costs. These companies studied the controllability and observability problems and instituted design rules into their design processes that, when followed, would guarantee that a circuit was testable. In the test department, where they also had complete control, they could utilize these added features with customized test development processes, gaining greatly enhanced levels of automation. One of the earliest and most prominent structured DFT schemes was IBM s Level Sensitive Scan Design (LSSD), which was developed in the 1970s.1 It is the precursor to what is called full internal scan technology now. In (greatly simplified) summary, LSSD design discipline requires every memory element (flip-flop or latch) to be constructed such that it obeys a testability protocol. This protocol allows two modes of operation: first, the normal operation of being a memory element in a design; and second, an operation for testing purposes, in which all memory elements can be connected into a serial shift register that can be loaded and unloaded by serial shifting. This makes every memory element a control point and an observation point within a circuit. No other memory elements are allowed in the design, e.g., no asynchronous feedback is allowed. This guarantees that circuitry between any control/observation point is combinatorial, not sequential (Fig. 54.2). As might be imagined, these rules were looked upon by designers as restrictions of their creativity. Ed Eichelberger of IBM, a major proponent of LSSD, happens to stand about 5.5 feet tall. When asked in 1977 how designers received the LSSD rules, he quipped that, at the start, he was over 6 feet tall. Structured testability is not easy to implement. It requires commitment from the whole organization, starting with management. The next piece of the puzzle was IBM s test generation software, which was able to automatically construct complete tests for combinatorial circuits (known as the D-algorithm and
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* The addition is modulo-2 yielding a single bit.Any single-bit error delivered to the three inputs of the exclusive OR will cause the output to change from its expected state. This spare input pin should be held to a 0 value when the IC is performing its normal function. A pull-down resistor to ground could assure this, whereas during test, a tester signal could assert a 1 value when needed for testing.
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