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General architecture of an 1149.1-compliant integrated circuit.
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As an example of this, boundary scan can be used to supply test patterns to nodes through a serialization process that a human would find laborious, but that is simple for a computer. When a set of patterns has been delivered (to control) and monitored (to observe) by the appropriate boundary register cells, we have uniquely identified each node with a signature. A defect such as a short will cause two nodes to have deviant signatures, as shown in Fig. 54.6. Software can correlate observed deviations with the known boundary scan structure of each IC and the board netlist to yield a diagnostic message.
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FIGURE 54.4 A collection (chain) of boundary scan devices can be used to test interconnections between ICs.
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FIGURE 54.5 A set of boundary scan ICs with interconnections. Note that four nodes do not have bed-of-nail access.
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The EXTEST capability can also be used during system testing to see if there are any system integration problems such as bad connections in backplanes and cabling. An IC designer may not see much attraction in EXTEST, but the 1149.1 standard offers other test modes that will allow a designer to access internal scan paths or built-in self-test functions. The 1149.1 standard s name has two parts, Standard Test Access Port being the first and crucially
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FIGURE 54.6 Interconnect testing drives unique patterns assigned to each node from drivers to receivers. In this case, a short is shown that creates a wire OR result.
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important one. It signifies that the standard anticipates being used as a standardized protocol for accessing any on-chip, board-level, or system-level testability scheme. In support of this, the standard is deliberately extensible, allowing clever designers to implement additional operational modes that can be used to solve unique testing problems. The 1149.1 standard has proven itself to be quite useful and it has several contributions. First, it allows the creation of software that can automatically write tests for boards where in the past the same level of test effectiveness was nearly impossible to achieve, and then only with weeks or even months of skilled labor. It is not uncommon to see a boundary scan board test prepared in a single day that otherwise might have taken weeks. Second, 1149.1 ICs can read their input pins and scan out the result. This allows diagnostic software to pinpoint the location of open solder problems where in the past an IC might have been falsely indicted as faulty. Third, it allows tests to be performed on digital circuits without 100 percent accessibility to board nodes. With the trend toward miniaturization of components making it difficult to provide full nodal access, boundary scan is allowing the elimination of many access points. Of course, not all points may be eliminated, so one must understand which are still necessary. Finally, because many industry segments are affected by the test problem, a standard offers a way for everyone to benefit. One can find a large number of applications and tools available to solve testing problems that would not have been possible without a standard.
IEEE 1149.4, Boundary-Scan for Mixed-Signal Circuits Boundary scan (1149.1) is a digital testability standard. However, there is also a trend in the superintegration of circuitry toward higher mixed-signal digital-analog content in our designs. The IEEE has developed a mixed-signal testability bus with a new standard 1149.4.4 6
This standard is constructed as a superset of 1149.1 boundary scan, adding two additional analog test pins to the definition. The goal of the standard is to support opens and shorts testing of mixed-signal boards and to provide the capability of making analog value measurements of discrete analog components such as resistors, inductors, and capacitors without direct nodal accessibility, that is, a full bed of nails. (See Fig. 54.7.) It has been likened to in-circuit testing without a bed of nails, which is again not without caveats. (The elimination of test access points will still have to be done with thoughtful deliberation.)
FIGURE 54.7 A mixed-signal circuit with some possible defects. IC pins marked A and D are analog and digital, respectively.
A mixed-signal device constructed with 1149.4 has the general architecture shown in Fig. 54.8. It is in many ways identical to an 1149.1 IC, but it has an additional analog test access port (ATAP) that is used to facilitate the control and observability of analog signals at device pins. The ATAP brings into the IC two additional analog signals that are used during testing. With 1149.4, digital device pins are treated exactly as done with an 1149.1 boundary register. Analog pins have an augmented structure called an analog boundary module (ABM) as part of the boundary register. The ABM allows an analog pin to be tested for simple shorts and opens (this is called 1149.1 interconnect test emulation) as well as allowing the injection and/or observation of analog signals via the ATAP. An ATE system can utilize the test resources in an 1149.4 IC as shown in Fig. 54.9. This requires the coordination of a digital test sequencer with analog test resources in this case, a current source and voltmeter. Pathways from these resources and through the 1149.4 IC can be used to make measurements on discrete analog components on a board, even with no bedof-nails access to the components. The pathways needed for a measurement are provided by silicon switches in the ABM. Because switches implemented this way have significant nonlinearity and nonnegligible impedances, these must be accounted for in the measurement processes. Figure 54.10 shows how an analog device can be tested with two measurements. First, the tester s current source is connected such that current can flow along AT1 into the IC. There it flows on the AB1 bus inside to the ABM connected to pin 1 of the IC. The current flows through Z and then into pin 2 of the IC. Pin 2 s ABM directs the current to ground, completing the current path. In Fig. 54.10(a), the ATE system s voltmeter is connected via the path AT2-AB2 to the ABM on pin 1, where it can observe the voltage at the top of Z. In Fig. 54.10(b), the voltmeter is switched to measure the voltage at pin 2, the bottom of Z. Subtracting the two voltage measurements gives the voltage drop across Z for a known current. Ohm s law gives us the value of Z, which we can check for the right value. This process works even with suboptimal silicon switches
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