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FIGURE 55.4 Cutaway drawing of a board resting on top of an in-circuit vacuum-actuated fixture, the bed of nails. The interface pins (the mechanical interface to the ATE pin electronics) are placed very close to reduce path lengths.
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the board. (Special clamshell fixtures allow nail access to both sides of a board.) The platen with board forms the movable top layer of a vacuum chamber. When vacuum is actuated, the platen with board moves down, depressing the nail springs and causing nail contact with board nodes. (Sometimes mechanical actuation is used in place of or to assist vacuum.) The nails are wired (typically with wire-wrap technology) to the stimulus/measurement resources of the tester. These resources contain mechanical relays that allow connection of various tester functions to a given nail. Once a tester has access to the nodes of a board, it can perform in-circuit (also called in situ) tests. The idea is to test components as if they are standing alone, while they in fact are part of a board circuit. The actual electrical processes used in in-circuit testing are explained in Sec. 55.5.
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LOADED BOARD TESTING
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Testing Boards for Specification Faults There is not much to add here because often, testing for specification defects is very similar to testing for performance faults. However, if for (say) contractual reasons, you are required to show your boards working as specified, you may be required to construct live situations where they are performing in a realistic system setting. Again, the extreme case of a missile shot on a test range could be involved. The question must be, is there an easier way
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IN-CIRCUIT TEST TECHNIQUES
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The problem of in-circuit testing can be subdivided into two main categories, analog in-circuit testing and digital in-circuit testing.
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Analog In-Circuit Test Analog in-circuit test addresses testing for shorts in the printed wire circuitry; analog components, passive devices such as resistors, inductors, and capacitors; and simple semiconductor components such as diodes and transistors.* Analog in-circuit testing is conducted without applying power to a board; that is, it is an unpowered test methodology. Shorts (unwanted connections between nodes) are tested for first because subsequent testing will profit from the assumption that shorts are not a factor, and subsequent testing may need to apply power to the board. Unpowered shorts testing may be accomplished by applying a small DC voltage to a node while all others are connected to ground. If current flow is observed that is below a computed threshold, then the node cannot be shorted to any of the grounded nodes. If the current flow is above the programmed threshold, there may be an unexpected path to at least one of the grounded nodes. The destination node(s) can be determined by linearly searching the grounded nodes for the current flow (this is slow) or by using half-splitting techniques (which are fast ) to determine the other node(s) the current is flowing to. When the algorithm has finished stimulating all nodes sequentially, it can declare which nodes are shorted and use x-y position data to show where to look for the problems. Typically, shorts are repaired before continuing with other tests because they may confuse the resolution of defects and may cause physical damage when the power is later turned on. Unpowered tests on analog components such as resistors, capacitors, inductors, etc., are performed next. Again, low stimulus voltages keep semiconductor junctions turned off. AC voltages are applied and phase-shifted currents are measured in order to deduce the values of reactive components (capacitors, inductors). For a simple measurement of a lone impedance R, apply a voltage to one terminal of the component (through the bed of nails) and connect a
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* Complex analog devices such as analog or mixed-signal ICs are not very amenable to analog in-circuit testing because they require power to be applied to the board. Simple diodes and single transistors can be tested by in-circuit stimulus that essentially examines the characteristics of their semiconductor junctions. The reason for using a small stimulus voltage (typically less than 0.2 V) is to prevent current flow through semiconductor junctions that may exist between nodes. This voltage will not turn on a junction. These junctions may exist in parasitic form within ICs and are not always documented. A half-splitting technique (also called a binary chop) is a fundamental algorithm of computer science. It works by successively considering half of a set of items (grounded nodes that are receiving current in this case) while removing the other half from consideration. It recursively divides sets repeatedly until only one item is left to consider. It has a complexity related to the logarithm (base 2) of the size of the original set of items. By comparison, a linear process has a complexity linearly related to the size of the original set. This component may not be alone in a physical sense, but because low stimulus voltages are used, other connected devices such as ICs may be electrically quiescent so that the component is electrically alone.
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