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FIGURE 55.12
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Capacitive leadframe testing used to find open solder joints.
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Figure 55.13 shows an equivalent circuit for capacitive opens test for a properly soldered IC lead and for an open solder condition. The capacitance C1 may be on the order of 100 fF (100 10 15 F), which is small enough to require sophisticated detection electronics to measure in the face of environmental noise. Now, if the IC leg is soldered to the stimulated board node, the correct capacitance will be measured. If the solder joint is open, then a second small capacitance C2 now exists in series with the first. This reduces the measured capacitance by a factor of 2 to 10. Capacitive leadframe test allows testing of complex ICs for solder opens without knowing what the ICs actually do and without applying power. The technique requires no complicated programming, and gives accurate resolution of solder defects. The technique has been extended to allow testing of solder integrity for connectors and switches. A fixture for capacitive leadframe testing is shown Fig. 55.14.
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FIGURE 55.13
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Equivalent circuits for fault-free and open solder conditions.
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FIGURE 55.14 A test fixture with board on a bed of nails, with clamshell top fixture containing capacitive sensor plates. Notice eight closely spaced sensor plates (right) that test for opens in eight (white) connectors on the board.
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TESTER COMPARISON
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Table 55.2 summarizes the types of tester for comparative costs and capabilities. A majority of manufacturers value good diagnostic resolution and fault coverage, so it is not surprising that in-circuit and combinational testers are in widespread use. Next in prevalence are the MDA testers, which are typically used where coverage and diagnostic resolution may be sacrificed
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TABLE 55.2 Costs and Capabilities of Various Testers Typical cost ($) 10 10
Tester type MDA In-Circuit Combo Functional Specification
Programming time 1 2 days 5 10 days 10 30 days 1 4 months Weeks to years
Diagnostic resolution Fair Best Best Fair Poor
Fault cover Poor Good Best Fair
Comments No digital coverage; requires known good board for programming. Fixturing is a major portion of preparation time. Functional test programming is a major portion of preparation time. Very high skill required for test preparation and interpreting results. Very high skill required for test preparation and interpreting results.
105 106 105 106 105 106 103 108
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for ease and speed of programming, usually in low-cost, high-volume products. Functional and specification testers are becoming rare, and are often only justified by the existence of contractual or regulatory requirements.
REFERENCES
1. W. A. Groves, Rapid Digital Fault Isolation with FASTRACE, Hewlett Packard Journal, vol. 30, no. 3, March 1979. 2. K. P. Parker, Integrating Design and Test: Using CAE Tools for ATE Programming, Computer Society Press of the IEEE, Washington, DC, 1987. 3. D. T. Crook, Analog In-Circuit Component Measurements: Problems and Solutions, Hewlett Packard Journal, vol. 30, no. 3, March 1979. 4. G. S. Bushanam et al., Measuring Thermal Rises Due to Digital Device Overdriving, Proceedings of the International Test Conference, Philadelphia, PA, October 1984, pp. 400 407. 5. V. R. Harwood, Safeguarding Devices Against Stress Caused by In-Circuit Testing, Hewlett Packard Journal, vol. 35, no. 10, October 1984.
RELIABILITY
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CONDUCTIVE ANODIC FILAMENT FORMATION
Dr. Laura J. Turbini
University of Toronto, Ontario, Canada
56.1 INTRODUCTION
The failure mode, conductive anodic filament (CAF) formation was first observed in the mid1970s by two different research groups, Bell Laboratories and Raytheon. Since then, further studies have led to an understanding of the factors that affect CAF formation. These include substrate choice, conductor configuration, voltage and spacing, processing, humidity and the storage, and use environment. CAF has been identified as a copper hydroxy chloride salt that causes catastrophic failure when it bridges because it has semiconductor properties. A CAF test method for multilayer boards has been developed by Sun Microsystems, and then introduced as an IPC test method. This chapter will explore these topics in more detail. It then identifies the printed wiring board (PWB) manufacturing tolerance limitations and makes recommendations for the design of CAF test coupons.
56.2 UNDERSTANDING CAF FORMATION
In the mid-1970s, Bell Labs researchers were concerned about potential failures of printed wiring boards intended for high-voltage switching applications. They reported1, 2 on accelerated life testing of flexible PWBs coated with ultraviolet (UV)-cured resin, and identified two new failure modes: conductive bridges between conductors on the surface, and conductive shorts through the substrate. AT&T Bell Labs test vehicle (see Fig. 56.1) was a flexible epoxy-glass PWB, 0.005 to 0.007 in. thick with comb patterns of 0.008 in. lines and 0.009 in. spaces. Some combs were biased on the surface and some were biased through the substrate. Processed boards, coated with conformal coating, were tested from 35 to 95 C, 25 to 95 percent relative humidity (RH), and direct current (DC) voltages up to 400 V. For accelerated testing at 85 C, 80 percent RH, and 78 V bias, failures occurred within two to five days. Bell Labs technicians identified two major failure modes that they described as causing catastrophic loss of insulation resistance due to the formation of conductive bridges between conductors. The first failure mode through-substrate shorts only occurred above 75 C and 85 percent RH and thus was not considered to be a problem at use conditions (see Fig. 56.2).
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