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FIGURE 57.23 PTH reliability test coupon. This coupon contains three sets of 1000 PTHs interconnected in series on four layers. Each set is a different hole size. The pad size is also varied. Similar designs are available from the IPC.
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57.6.2.2 Mechanical. Printed circuit boards are rarely subjected to mechanical tests that could cause electrical failures; however, adhesion of both Cu and solder mask to the laminate is critical and is often tested. Loss of solder mask adhesion can provide a place for corrodants and moisture to accumulate, which can be the cause of electrical failures when the board is exposed to temperature and humidity. Adhesion is commonly tested using the peel test described in IPC-TM-650, Method 2.4.28. The simplest version of this test is conducted by scribing the adherent and dividing it into small squares. If the Cu or solder mask pulls off with a piece of tape with strong adhesive, the adhesion is inadequate. More quantitative tests that measure the actual peel strength are performed primarily by laminate and solder mask suppliers. 57.6.2.3 Temperature, Humidity, Bias. These tests are designed to promote corrosion on the PCB surface and conductive anodic filament growth, either of which can cause insulation resistance failures. Surface insulation tests utilize two interleaved Cu combs with an imposed dc bias across the combs. These combs may be designed into existing boards or a coupon such as the IPC-B25 test board shown in Fig. 57.24 may be used.The measured resistance (ohms) from the comb pattern can be converted to surface resistivity (ohms per square) by multiplying the measured
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RELIABILITY OF PRINTED CIRCUIT ASSEMBLIES
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FIGURE 57.24 Test coupons used to check moisture, insulation, and metal migration resistance: (a) the IPC-B-25 test board, used to qualify the process; (b) The Y coupon, designed to be incorporated into production boards for statistical process control. From IPC-SM-840.
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resistance by the square count of the pattern. The square count is determined geometrically by measuring the total length of the parallel traces between the anode and cathode and dividing by the separation distance. Special precautions are needed to make accurate measurements of insulation resistance.42 Measurements of resistance above 1012 are very difficult and require careful shielding. Measurements of resistance below 1012 can be conducted in most laboratory environments if certain precautions are taken. The actual tests are usually conducted at elevated temperature and humidity with an applied dc bias. A test for moisture and insulation resistance of bare printed circuit boards is included in IPC-SM-840A. The severity of the test depends on the intended use environment; for typical commercial products (Class 2), the test is conducted at 50 C, 90% RH, and 100 Vdc bias for 7 days. The minimum insulation resistance requirement is 108 . The military test procedure for moisture and insulation resistance is specified in MIL-P-55110.43 The moisture resistance test should be conducted in accordance with MIL-STD-202, Method 106, with
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applied polarization voltage (100 Vdc) and Method 402, Test condition A.44 IPC-SM-840A also includes a test for electromigration resistance. The test is conducted at 85 C/90% RH at a 10 Vdc bias with a limiting current of 1 mA for 7 days. A significant change in current constitutes a failure. The samples are also microscopically inspected for evidence of electrolytic metal migration. A common test for dendritic growth due to flux residues is 85/85/1000 h at 20 Vdc bias. These tests are empirically based; however, several investigators have attempted to develop acceleration factors for these and similar tests.45,46 57.6.3 Printed Circuit Assembly Reliability Tests 57.6.3.1 Thermal. Most thermal cycling of PCAs is intended to accelerate solder joint thermal fatigue failures. In spite of the existence of an IPC standard, there is no standard accelerated test today that is suitable for all component and substrate combinations and all service environments. There are several acceleration models in the literature, each of which seems to fit the data well in at least some situations. All are based on a combination of empirical observations and fundamental arguments under simplifying assumptions. This topic remains a subject of active research since in some cases the predictions are significantly different. There is also a move to replace thermal cycling tests with mechanical cycling tests, which could be conducted in a shorter period of time; however, these tests are even further from standardization. Finally, for some components which dissipate a significant amount of power (usually 1 W or more), cycling the ambient temperature (which heats from the outside) may give quite different results from power cycling (in which heating occurs from the inside); for example, the failure location may shift from corner joints (which see the largest displacements) toward solder joints located near the chip (because they are hotter). Consequently, while thermal cycling will be adequate for most ASICs, memory chips, etc., power cycling should be considered for microprocessors, particularly those that dissipate more than a few watts. Thermal shock testing is commonly used to test components, but it is not necessarily a substitute for thermal cycling. Because the temperature ramp is extremely rapid and the dwell at the extremes is generally short, there is little time for creep; consequently, the number of cycles to failure is increased. Furthermore, the rapid temperature change can induce differential thermal stresses that may be larger than those experienced during thermal cycling. These stresses can induce early failures, particularly if the failure is not in the solder. There are some principles for designing thermal cycling tests to accelerate solder fatigue that seem to be generally agreed on. The following guidelines apply to gradual temperature cycling due to ambient heating inside a unit (e.g., due to power dissipation). If the unit will be subjected to extreme temperatures or thermal shock in service, these generalizations may not apply. A sample cycling protocol is shown in Fig. 57.25.
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The maximum test temperature should be below the Tg of the printed circuit board, for FR-4 below about 110 C. At Tg, the CTE of the board increases rapidly, but many other properties also change; for example, the elastic modulus of the board decreases. To avoid approaching the melting temperature of the solder and changing the mechanism of solder creep, the maximum temperature should also be kept below about 0.9Tm, where Tm is the melting temperature of the solder in Kelvin. For eutectic Sn-Pb solder, Tm is 137 C, well above Tg. But for printed circuit board materials with high Tg values or low-meltingtemperature solders, this restriction may take precedence. Using a peak temperature above these limits results in unpredictable acceleration. The minimum temperature should be high enough that creep is still the primary deformation mechanism of the solder, that is, at least 0.5 Tm, or 45 C for eutectic Sn-Pb solder. Many investigators prefer a higher minimum temperature ( 20 or 0 C) to ensure that creep occurs fast enough to relieve the imposed shear stress during the allowed dwell time. Using too low a minimum temperature may seem to increase the acceleration factor (increased T ) while actually decreasing it (decreased ), resulting in an overly optimistic life prediction.
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