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RELIABILITY OF PRINTED CIRCUIT ASSEMBLIES
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One acceleration model that is applied is the modified Eyring model, which was developed for moisture-induced corrosion in plastic packages: t50% = A exp where t50% A, B, C, and D Ea k T Hr V = = = = = = = Ea kT exp C Hr Dexp V B (57.4)
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time at which 50 percent of parts have failed empirical constants thermal activation energy Boltzmann constant temperature in degrees Kelvin relative humidity reverse-biasing voltage41,46
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The time to failure is also dependent on the concentration of ionic contaminants. The default industrial ionic contamination limit comes from MIL-STD-28809A; it is the equivalent of 3.1 g/cm2 of NaCl. For small plastic packages, enough data have been collected to show that an empirical acceleration factor for temperature and relative humidity AFT,Hr applies: AFT, H r = 2(T+Hr)test (T+Hr)service where AF = acceleration factor T = temperature in C Hr = relative humidity in percent46,49 (57.5)
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The rule of thumb for the effect of reverse bias is very device-specific; the following relationship was established for 20-V Schottky diodes in SOT-23 packages:46 AFV = 7700 exp V 12.32
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When both acceleration factors apply, the total acceleration factor is: AFtotal = (AFT, Hr )(AFV)
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Reliability of electronic assemblies is a complex subject. This chapter has touched on only one aspect of the problem: understanding the primary failure mechanisms of printed circuit boards and the interconnects between these boards and the electronic components mounted on them. This approach provides the basis for analyzing the impact of design and materials choices and manufacturing processes on printed circuit assembly reliability. It also provides the foundation for developing accelerated testing schemes to determine reliability. It is hoped that the fundamental approach will enable the reader to apply this methodology to new problems not yet addressed in mainstream literature.
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1. M. A. Oien, Methods for Evaluating Plated-Through-Hole Reliability, 14th Annual Proceedings of IEEE Reliability Physics, Las Vegas, Nev., April 20 22, 1976. 2. K. Kurosawa, Y. Takeda, K. Takagi, and H. Kawamata, Investigation of Reliability Behavior of Plated-Through-Hole Multilayer Printed Wiring Boards, IPC-TP-385, IPC, Evanston, Ill., 1981.
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PRINTED CIRCUITS HANDBOOK
3. IPC-TR-579, Round Robin Reliability Evaluation of Small Diameter Plated Through Holes in Printed Wiring Boards, Institute of Interconnecting and Packaging Electronic Circuits, Lincolnwood, Ill. The IPC recently initiated a second round robin study, the results of which should be available in about 1996. 4. F. Fehrer and G. Haddick, Thermo-mechanical Processing and Repairability Observations for FR-4, Cyanate Ester and Cyanate Ester/Epoxy Blend PCB Substrates, Circuit World, vol. 19, no. 2, 1993, pp. 39 44. 5. D. B. Barker and A. Dasgupta, Thermal Stress Issues in Plated-Through-Hole Reliability, in Thermal Stress and Strain in Microelectronics Packaging, J. H. Lau (ed.), Van Nostrand Reinhold, 1993, pp. 648 683. 6. IPC-TM-650, Method 2.4.8. 7. L. D. Olson, Resins and Reinforcements, in ASM Electronic Materials Handbook, Vol. 1: Packaging, ASM International, Materials Park, Ohio, 1989, pp. 534 537. 8. D.W. Rice, Corrosion in the Electronics Industry, Corrosion/85, paper no. 323, National Association of Corrosion Engineers, Houston, 1985. 9. J. J. Steppan, J. A. Roth, L. C. Hall, D. A. Jeannotte, and S. P. Carbone, A Review of Corrosion Failure Mechanisms during Accelerated Tests: Electrolytic Metal Migration, J. Electrochemical Soc., vol. 134, 1987, pp. 175 190. 10. D. J. Lando, J. P. Mitchell, and T. L. Welsher, Conductive Anodic Filaments in Reinforced Polymeric Dieletrics: Formation and Prevention, 17th Annual Proceedings of IEEE Reliability Physics Symposium, San Francisco, April 24 26, 1979, pp. 51 63. 11. How to Avoid Metallic Growth Problems on Electronic Hardware, IPC-TR-476, Sept. 1977. 12. B. Rudra, M. Pecht, and D. Jennings, Assessing Time-of-Failure Due to Conductive Filament Formation in Multi-Layer Organic Laminates, IEEE Trans. CPMT-Part B., vol. 17, August 1994, pp. 269 276. 13. J. W. Price, Tin and Tin Alloy Plating, Electrochemical Publications, Ayr, Scotland, 1983. 14. D. R. Gabe, Whisker Growth on Tin Electrodeposits, Trans. Institute of Metal Finishing, vol. 65, 1987, p. 115. 15. C. Lea, A Scientific Guide to Surface Mount Technology, Electrochemical Publications, Ayr, Scotland, 1988. 16. J. H. Lau (ed), Solder Joint Reliability: Theory and Applications, Van Nostrand Reinhold, New York, 1991. 17. D. R. Frear, S. N. Burchett, H. S. Morgan and J. H. Lau, eds., Mechanics of Solder Alloy Interconnects, Van Nostrand Reinhold, New York, 1994. 18. J. H. Lau (ed.), Thermal Stress and Strain in Microelectronics, Van Nostrand Reinhold, New York, 1993. 19. S. Burchett, Applications Through-Hole, in The Mechanics of Solder Alloy Interconnects, op. cit., pp. 336 360. 20. E. Suhir and Y.-C. Lee, Thermal, Mechanical, and Environmental Durability Design Methodologies, in ASM Electronic Materials Handbook, Vol. 1: Packaging, op cit. 21. IPC-D-279, Design Guidelines for Reliable Surface Mount Technology Printed Board Assemblies, to be published. 22. L. T. Manzione, Plastic Packaging of Microelectronic Devices, Van Nostrand Reinhold, New York, 1990. 23. ASM Electronic Materials Handbook, Vol. 1: Packaging, op. cit. 24. R. R. Tummala and E. J. Rymaszewski (eds.), Microelectronic Packaging Handbook, Van Nostrand Reinhold, New York, 1989. 25. For a more comprehensive list of components that may be at risk, see IPC-D-279, Design Guidelines for Reliable Surface Mount Technology Printed Board Assemblies, App. C, to be issued. 26. L. Zakraysek, R. Clark, and H. Ladwig, Microcracking in Electrolytic Copper, Proceedings of Printed Circuit World Convention III, Washington, D.C., May 22 25, 1984.
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