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COMPONENT-TO-PWB RELIABILITY THE IMPACT OF DESIGN VARIABLES AND LEAD FREE
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58.1 INTRODUCTION
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The mandated conversion to lead free assemblies has led to the convergence of several critical issues in the microelectronics industry. The conversion has further compounded several other factors that have been pushing the envelope in Component to Printed Wiring Board (PWB) reliability, including
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Radical increases in package-to-board input/output (I/O) Rapid reduction in interconnect pitch Overall rise in surface-mount component density Higher speeds and correspondingly higher heat dissipation
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All of these factors pose tremendous challenges with respect to reliability, and they cause complex design tradeoffs that must be considered while maintaining product reliability at required levels. Time to market and aggressive product life cycle pressures also require PWB designers to consider the impact that alternate designs and material sets may have on reliability, in a rapid fashion. The PWB designer is faced with myriad packaged device types, field use environments, connectors, PWB materials, cost considerations, and real estate restrictions, which all must be optimized without degrading system reliability. Designers need tools to assess experimental reliability data, transform laboratory results into actual field loading conditions, and rapidly assess the reliability of different PWB layouts, material sets, and package types. Engineers must also have the capability for addressing complex loading conditions such as mini- and power-cycles and the knowledge of how they impact interconnect performance.
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Copyright 2008 by The McGraw-Hill Companies. Click here for terms of use.
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PRINTED CIRCUITS HANDBOOK
This chapter focuses on the design variables that impact the reliability of PWB-to-package interconnect (second- and third-level interconnect) of grid array devices and the impact of lead-free conversion on these design variables. Some of the critical variables discussed in depth include:
Double-sided construction PWB stiffness effect Multiple packages in a small area Package and PWB warpage; assembly and reliability challenges Solder joint geometry; assembly and reliability challenges Package and PWB pad size Heatsink design and attachment Package and PWB surface finish; Black Pad, Brittle Failure, and Kirkendall voiding PWB electrical test architecture Carrier chassis design Package design parameters such as overall size, silicon technology, ball array, ball size/pitch, heat spreader/stiffener, material selection, die/package aspect ratio, substrate material, low-k dielectrics and so on
The chapter is broken up into the following sections. Section 58.2, Packaging Challenges, outlines several of the performance challenges faced by next generation packages, and the key technical drivers behind these challenges. Section 58.3, Variables That Impact Reliability, contains a discussion of the common design variables that could impact the reliability of a product; ranging from PWB design rules to package design parameters. The failure modes relating to the choice of different package design parameters are outlined, along with recommendations on ways to mitigate different manufacturing and test-related failure mechanisms.
PACKAGING CHALLENGES
The reliability of many types of leadframe components (see Figs. 58.1 and 58.2) has been assessed in great detail.1 Figure 58.3 shows the typical definitions of interconnect levels in assemblies.While leadframe devices are by no means infinitely reliable at the first and second level interconnects, they have historically posed a lesser risk than grid-array packaged components, such as ceramic ball grid arrays (CBGAs), plastic ball grid arrays (PBGAs), ceramic solder column carriers
FIGURE 58.1 Diagram of a quad flat pack. Note the copper (Cu) leads that are attached by gold wire bonds to the die. This is the primary (or first-level interconnect) between the die and the package. The second-level interconnect will be created when the Cu leadframe is soldered to a motherboard via some type of surface-mount attach process. (Courtesy of Amkor Technology, Inc.)
COMPONENT-TO-PWB RELIABILITY
FIGURE 58.2 J-leaded device oriented bottom side up. (Reprinted with permission from J. Lau, Ball Grid Array Technology, McGrawHill, New York, 1995, p. 20.)
1st Level Interconnect
Silicon
2nd Level Interconnect
Package Substrate Module Substrate
3rd Level Interconnect
FIGURE 58.3 First-, second- and third-level interconnects defined, employing a flip-chip assembly as an example. The first-level interconnect is the primary connection between the silicon die and the package substrate. In this example it is created by the solder bumps between the die and the package. The second-level interconnect in this example is the next level of connection between the package substrate and the module substrate. The third-level interconnect in this example is created when the solder balls on the bottom side of the module substrate are attached via SMT to the PWB.
(CSCCs), flip-chip ball grid arrays (FCBGAs), and chip scale packages (CSPs).This is because the compliant leadframe in leadframe packages can absorb the differential strain induced in the solder joints, due to the mismatch in thermal expansivity between the silicon chip and the PWB. Ball grid array packages, on the other hand, rely entirely on the discrete solder balls absorbing the differential strain. Depending on the package construction, the solder joints at critical high strain locations could fail early, resulting in lower long-term reliability of the assembly. Figure 58.4 shows various grid array packaged devices. To meet increasing I/O density requirements, many of these types of packages are either increasing in body size, decreasing in pitch, or both, to a point where the standard reliability envelope is being pushed to extreme levels.Additionally, most grid array packaged devices are high in cost (in many instances the grid array packaged devices are the most costly component on a printed circuit assembly) and thus cannot be deployed in a redundant design. Lack of redundancy creates critical path single points of failure (SPOFs). Failure of one of these devices can lead to catastrophic system-level failures. The proliferation of high-I/O, small-pitch grid array packaged devices throughout the electronics industry impacts almost all PWB engineers because any design has a high probability of containing one or more of these types of components.
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