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FIGURE 58.24 Schematic of ICT loading conditions.
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made as uniform as possible. Several ICT fixtures have push fingers on the top side, which push down on the board, countering the force of the test probes. The use of push-pins or push-fingers on the top side of the board is not recommended. Push fingers induce localized stress concentrations, resulting in high strain in their immediate vicinity. If used, push fingers should not be placed close to package corners. For some generic recommendations on ICT test point layout, refer to IPC7351.15 An alternative to push fingers is the use of a Milled City or zero-flex top plate on the top side. This is basically a rigid metal plate which has a negative image of the entire board milled out. Thus, as opposed to having several push fingers, the entire board is pressed against the Milled City plate. This significantly reduces local stress concentration, and could potentially be used to enable PCBAs to withstand more test points. Milled City plates are expensive, but considering the cost of line stops and customer-related issues due to strain-induced failures in ICT, the non-recurring cost of the Milled City is a worthwhile investment. 58.3.12.1 Effect of Lead-Free Conversion. The conversion to lead-free solder has given even more prominence to this issue. With lead-free solders, a higher temperature organic solderability preservative (OSP) could be used. As a result, it could take more force to establish contact with the test pads. This translates to higher force applied to the PCBA. Moreover, the effect of mechanical bending on lead-free solders is yet to be fully characterized. Thus, there is a greater need to characterize the mechanical force applied on lead-free assemblies. For the same applied force, the strain on thinner PWBs is higher than that on thick PWBs. Thus, this is more critical on assemblies with relatively thin boards (<93 mils thick). However, depending on the package, warpage, surface finish, and number of test points, it could also be seen on thick boards. Strain gage characterization should be performed on fixtures with actual boards, in order to verify that excessive strains are not applied on critical components. In an effort to standardize strain characterization, the JEDEC/IPC 970425 test method was published in June 2005. This test method outlines the procedures and best practices relating to strain measurement in a manufacturing environment. 58.3.13 Package Design Parameters A key factor that impacts second-level interconnect reliability is the package itself. Although the primary function of the package is to pass signals, power, and ground from the silicon device to the PWB, the package also provides protection for the silicon and enables a more robust interconnect than a direct chip attach. The critical package design parameters which can have a significant impact on the reliability of the solder joints are discussed in this section. 58.3.13.1 Overall Dimensions and Distance from Neutral Point (DNP). Package size continues to grow as the number of I/Os increase to meet the demands of ever increasing IC functionality.As IC complexity increases, memory is embedded in devices, while as silicon feature sizes decrease, I/O counts continue to be driven upward. Package dimensions have surpassed 50 mm. Package layer counts for both ceramic and plastic material sets continue to increase rapidly. In addition to the solder joint geometry issues outlined in Sec. 58.3.8, increases in overall size tend to coincide with increases in the distance from the center of the package to the outer ball (see Fig. 58.25). This dimension is referred to as the Distance from the Neutral Point (DNP). As DNP increases, the amount of stress and subsequent damage inflicted on solder joints increases, especially during thermal cycles encountered in field environments.Thus packages with larger DNPs (and with all other material and design parameters equivalent) will have lower interconnect reliability. This is crucial when assessing second-level reliability data. Most packaged IC suppliers qualify their products by thermal cycle experiments. The most common board level temperature cycling methodology used across the industry is outlined in IPC 9701.6 The resistance in each solder joint is typically monitored in real time by incorporating a daisy-chain package and some type of data acquisition system. The end results of
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