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58.3.13.7 Die/Package Aspect Ratio. The size of the silicon die relative to the package body size could significantly impact the reliability of the package. This is especially applicable to PBGA packages. The larger the die relative to the package, the higher the CTE mismatchdriven strains imparted to the second level solder joints.28 The degree of impact varies with package body size and absolute die size. 58.3.13.8 Package Substrate Material. The choice of package substrate material can have a large impact on solder joint reliability. Some substrates require employing solder ball alternatives (such as the ceramic solder column carriers shown in Fig. 58.4) or even the elimination of a soldered solution due to interconnect reliability considerations. A wealth of information regarding ceramic and plastic substrates can be found in the literature.26,29,30 This section focuses on the impact of those materials on solder joint reliability. The two key material properties of a substrate that impact interconnect reliability are modulus of elasticity (E) and coefficient of thermal expansion (CTE). Modulus of elasticity is defined as the ratio of stress to strain and can be used to describe a material s ability to resist deformation when subjected to an applied load. CTE relates the change in length of material when heated or cooled and can be used to describe a material s deformation when subjected to temperature changes. Reference 31 contains detailed discussions of modulus of elasticity and coefficient of thermal expansion. A tremendous amount of material property data can be found in the literature.26,29,30 Fig. 58.31 contains a sketch of a simplified solder joint interconnect. Note that the driving force for solder joint fatigue during field use is the coefficient of thermal expansion mismatch between the assembled package and the PWB. Additionally, the modulus of elasticity of the substrate can impact the fatigue life of solder joints by increasing (or decreasing) the driving force that is imparted to the solder interconnect.
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FIGURE 58.31 Simplified CTE mismatch effects. As the temperature increases, the PWB expands at a higher rate than the package due to the package having a lower effective CTE. As the temperature decreases, the opposite effect is observed.
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Ceramic materials provide excellent CTE match between the die and package, which then reduces the risk of first-level solder bump failure in flip-chip applications. Unfortunately, this superb CTE match between the ceramic and the silicon die creates a large CTE mismatch between the ceramic package and the PWB. This CTE mismatch creates severe stress on the second level interconnects (see Fig. 58.31). This CTE mismatch, combined with DNP issues
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(previously discussed), limits ceramic BGA body sizes to approximately 32 32 mm. Ceramics with larger body sizes typically employ solder columns (Fig. 58.4) or compression-type sockets for second-level interconnect. The CTEs of plastic packages tend to match the CTEs of PWBs fairly well. This CTE match allows for larger package body sizes to be employed when using a laminate-based BGA than with a ceramic package. It is crucial to note that many other variables independent of second-level reliability must be taken into consideration when selecting a package. Power requirements, signal integrity, first-level reliability (interconnect between the die and package), and cost must all be balanced when selecting the correct package for a specific application. 58.3.13.9 Impact of Low-k Dielectrics. Continued miniaturization and integration has led to the need for a multilevel interconnect layout to minimize the time delay due to parasitic resistance (R) and capacitance (C). The improvement in gate level device speed is negated by the propagation delay at the metal interconnects because of the increased RC time constant.32 For instance, the RC delay of long interconnections contributes up to 50 percent of the time delay in devices with a gate length of 250 nm or less.33 A reduction in the RC time constant requires the use of low resistivity interconnect materials and low capacitance interlayer films. The capacitance is a function of the material dielectric permittivity ( i), area (A), and thickness (d). (C = i A/d). Increasing the area would require increased interconnect lengths, which in turn would result in high resistance. The thickness can also not be increased because it also increases resistance and poses manufacturing challenges in consistently filling the interlayer layers. Consequently, the dielectric constant (k) needs to be reduced. Hence the need for low-k materials. In addition to having a low dielectric constant, ideal low-k materials need to have low residual stress, high planarization capability, high gap-filling capability, low deposition temperature, and ease of process integration.32 A list of possible candidates for low-k materials is outlined in Table 58.3.33
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TABLE 58.3 Typical Low-k Materials33 Determinant Vapor-phase deposition polymers Materials Fluorosilicate glass (FSG) Parylene N Parylene F Black diamond (C-doped oxide) Fluorinated hydrocarbon Teflon-AF HSQ/MSQ Polyimide SiLK (aromatic hydrocarbon polymer) PAE [poly(arylene ethers)] Fluorinated amorphous carbon Xerogels (porous silica) Dielectric constant 3.5 4.0 2.6 2.4 2.5 2.7 3.0 2.0 2.4 1.93 2.8 3.0 2.7 2.9 2.7 2.6 2.1 1.1 2.0
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