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However, several of the new low-k materials are porous and structurally weak. This poses several challenges in the back-end assembly process: poor adhesion, residual stresses in the inner layer dielectric (ILD) films, and so on. In addition to optimizing and better monitoring the wafer-sawing process, the effect of chip-to-package interactions also needs to be characterized. The choice of material set, underfill, substrate, lid material, and so on could impact the reliability of the low-k dielectric. In flip-chip BGA (FCBGA) packages, the choice of underfill material in particular has been the subject of considerable interest.34 36 In addition to a new material set and design rules, several packaging assembly manufacturers have evaluated the use of low glass transition
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temperature (Tg) underfills to reduce the stresses imparted to the silicon. However, while using a low Tg underfill may minimize the stresses on the low-k, it could in turn transfer the stresses elsewhere, such as in the first-level interconnect.37 Moreover, the effect of the material set on ILD delamination and solder joint reliability may be different when the free standing package is stressed, as opposed to when it is mounted on a printed circuit board and then stressed. In wirebond BGA packages, the effect of the wirebonding process on the low-k dielectric needs to be characterized.38 In addition, the choice of mold compound material (modulus and CTE) could also impact the long term reliability of the low-k dielectric in the fully assembled package. The package with the selected material set should be subjected to component level and second level temperature cycling, followed by scanning acoustic microscopy (SAM) to ensure that there are no delamination-induced failures in the low-k dielectric or other critical interfaces.
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1. J. H. Lau (ed.), Solder Joint Reliability: Theory and Applications, Van Nostrand Reinhold, New York, 1991. 2. S. B. Park, Rahul Joshi, and Lewis Goldmann, Reliability of Lead-Free Copper Columns in Comparison with Tin-Lead Solder Column Interconnects, Electronic Components and Technology Conference, 2004, pp. 82 89. 3. IPC-SM-785, Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments, 1992. www.ipc.org. 4. Jin-Young Kim, Won-Joon Kang, Yoon-Hyun Ka, Yong-Joon Kim, Eun-Sook Sohn, Sung-Su Park, Jae-Dong Kim, Choon-Heung Lee, Akito Yoshida, and Ahmer Syed, Board Level Reliability Study on Three-Dimensional Thin Stacked Package, Electronic Components and Technology Conference, 2004, pp. 624 629. 5. Rocky Shih, Sam Dai, Francois Billaut, Sue Teng, Mason Hu, Ken Hubbard, The Effect of Printed Circuit Board Thickness and Dual-sided Configuration on the Solder Joint Reliability of Area Array Packages, International Microelectronics and Packaging Society (IMAPS), 2004. 6. IPC 9701, Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments, IPC, January 2002. www.ipc.org. 7. S. Ehrler, Compatibility of Epoxy-based PCBs to Lead-Free Assembly, Circuitree, 1st June 2005. 8. S. Ehrler, Comparison of High-Tg-FR-4 Base Materials, IPC-Expo & Conference, Long Beach, CA, 24 26th March 2003. 9. Mudasir Ahmad, Sue Teng, Jie Xue, Effect of Underfill Material Properties on Low- k Dielectric, First and Second Level Interconnect Reliability, IMAPS Conference on Device Packaging, Scottsdale, AZ, 2006. 10. JEDEC Design Standard, Design Requirements For Outlines Of Solid State And Related Products, JEDEC Publication 95, Design Guide 4.14, Ball Grid Array Package (BGA), Issue D, December 2002. www.jedec.org. 11. Mudasir Ahmad, Ken Hubbard, Mason Hu, Solder Joint Shape Prediction Using a Modified Perzyna Viscoplastic Model, ASME Journal of Electronic Packaging, 2005, 127(3), pp. 290 298. 12. JEDEC Standard, JESD22b112, High Temperature Package Warpage Measurement Methodology, May 2005. www.jedec.org. 13. Benlih Huang, Ning-Cheng Lee, Conquer Tombstoning in Lead-Free Soldering, IPC Printed Circuits Expo, SMEMA Council, APEX Designers Summit 2004, pp. S27-1 S27-7. 14. Lei L. Mercado, Vijay Sarihan, Yifan Guo, and Andrew Mawer, Impact of Solder Pad Size on Solder Joint Reliability in Flip Chip PBGA Packages, IEEE Transactions On Advanced Packaging, Vol. 23, No. 3, August 2000, pp. 415 420. 15. IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard, IPC, February 2005. www.ipc.org. 16. Marie S. Cole, J. Jozwiak, E. Kastberg, G. Martin, Compressive Load Effects On CCGA Reliability, SMTA International, September 2002.
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