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Permittivity, 8.7. See also Dielectric constant Photoimageable material, 22.7 Phototools, in Etching, 34.20 Pin Grid Array (PGA), 3.8 3.11 Pink ring (Halo), 52.33 Plastic Quad Flat Package (PQFP), 3.7, 3.8 Plating, preparation for, 28.1 28.11 Board preparation, 28.1 28.10 Direct metallization, 30.1 30.11 Electroless copper deposition, 28.8 28.11 Electroplating, 29.1 29.30 Etchback, 28.5 28.7 Feed water, 28.3 28.5 Flowchart, for PWB, 28.2 Multilayer preprocessing, 28.4 28.8 Preparing boards for plating, 29.1 28.12 Process decisions, 28.1 28.3 Smear removal, 28.5 28.7 Surface finishes, 32.1 32.10. See also Direct metallization, Electroplating, Surface finishes, specific metal Platinum metals, 29.26, 29.27 Polyimide, 27.11 Prepreg Identification scheme, 6.17 Manufacturing processes, 6.17 6.24 Options, 9.9 Styles, glass, and resin combinations. See Laminate Prepreg testing, 12.1 12.20. See also Laminate evaluation Press-fit, 13.16. See also, Press-fit connections Press-fit connections, 49.3 49.17 Advantages of, 49.3, 49.4 Assembly process, 49.11 Design issues, 49.6, 49.7, 49.14, 49.15 Equipment, 49.10, 49.11 Inspection, 49.16, 49.17 Lead-free issues, 49.7 Materials issues, 49.7 49.8 Pin configurations, 49.4 49.6 Press routines, 49.12 49.14 PWB design for, 49.14 Requirements for, 49.6, 49.7 Rework, 49.13, 49.14 Surface finish, 49.8 49.10 Testing, 49.16, 49.17 Printed Circuit Boards (PCB). See Printed Wiring Boards (PWB) Printed Wiring Assembly (PWA), testing of. See Assembled board testing Printed Wiring Boards (PWB) Additive, 5.2, 5.3, 31.1 31.15 Classifications, 5.1 5.3 Discrete-wire, 5.3, 5.4 Double-sided boards, 5.7, 5.8 Technologies of, 5.7 Flexible, 5.5 Graphical, 5.3, 5.4, 5.6 5.9 Molded, 5.10 Multilayer boards (MLB), 5.8, 5.9 High density, 5.8, 5.9
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Layer count, 5.8 Vias for, 5.8, 5.9 Non-organic substrate, 5.3 Organic substrate, 5.3 Physical characteristics, 13.1 13.25 Plated-through-hole (PTH), 5.10 5.13 Rigid, 5.5, 5.6 Single sided boards, 5.6, 5.7 Fabrication of, 5.6, 5.7 Materials, 5.6 Subtractive, 5.2, 5.3 Types of, 5.1 5.14 See also Printed wiring board types Process standards, A1 A7 PTFE, 7.7, 27.14 Punch forming, 13.22 PWB. See Printed Wiring Boards Analog, 13.3 13.6 Characteristics of analog, 13.3 13.6 Characteristics of digital, 13.6 13.9 Choosing a package type, 13.24, 13.25 Component attachment methods, 13.14, 13.15 Density elements, 2.4 Design of, choosing package type, 13.24, 13.25 Design process, 14.1 14.12 Digital, 13.6 13.9 Embedded components, 13.21 13.23 Fabrication methods, 13.22 13.24 Materials choices, 13.18 13.21 Microwave, 13.3 13.6 Trace capacitance, 13.4 13.6 Trace impedance, 13.4 13.6 Types of, 13.9 13.14 Backplanes, 13.12 Discrete wire, 13.10 Double-sided, 13.9, 13.10 Flexible circuits, 13.10 Flex-rigid, 13.12 Hybrids, 13.10 Multichip modules, 13.12 13.14 Multilayer, 13.10 13.12 Multiwire, 13.10 Single-sided, 13.9, 13.10 PWB board acceptability. See Fabricated board acceptability PWB fabrication Machining, 35.1 35.15 Blanking, 35.4 Punching, 35.1 35.4 Routing, 35.6 35.13 Sawing, 35.5, 35.6 Scoring, 35.13 35.15 Shearing, 35.4, 35.5 Design review, 20.7 20.15 Design rule check, 20.20 20.22 Design input, 20.15 20.18 Documentation, 20.16 20.18 Information required, 20.2 20.4 Information transfer, 18.1 18.23 Materials requirements, 20.8, 20.9 Panelization, 20.11 20.14 Process requirements, 20.9 20.11
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INDEX
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Routing, 35.6 35.13 Scoring, 35.13 35.15 See also Routing Punching holes, 35.1 35.3 Repair and rework, 40.57 40.64, 48.1 48.7 Resistance, trace, 13.6 Resistive foils, 21.4 21.8 Resistor integration, 3.23 3.25 Resistors, buried, 21.2 21.10 Restriction of Hazardous Substances, 1.1 1.0. See also RoHS Reverse Osmosis (RO), 28.4 Rhodium plating, 29.26, 29.27 Rigid/flexible circuits, 65.1 65.7 Blind vias, in, 65.6, 65.7 Bookbinder construction, 65.7 Build-up process, 65.6 Constructions, 65.1 65.3 Manufacturing process, 65.4 65.7 Materials, 65.3, 65.4 RoHS, 1.1 1.10, 10.1, 10.2 Assembly issues, 40.7 Compliance, 1.4, 1.5 Flexible circuit, 62.17 Flux, issues with, 43.1, 43.2 Impact on Electronics industry, 1.6 1.10 Laminates, impact of, 10.1 10.18, 11.1 11.18, 12.1, 12.2 Products affected, 1.4 Products exempted, 1.5, 1.6 Surface mount assembly, and, 40.18 Solders, lead-free, 45.5 45.11 Roll forming, 13.22, 13.23 Routers (CAD), 14.8, 14.9 Routing, 35.6 35.13 CNC operation, 35.6 35.8 Cutter issues, 35.9 35.11 Laser routing, 35.11 Pin routing, 35.6 Tooling, 35.11 RS-274X, 37.16 Ruthenium plating, 29.27 Scoring, 35.13, 35.14 Semi-conductor components I/O termination methods, 2.10, 2.11. Packages, 2.10 See also Direct Chip Attach, Chip Scale Packages, Semi-conductor packaging Semi-conductor packaging, 3.1 3.22. See also Advanced Packaging Advanced, 4.1 4.30 Density trends, 3.2 Frequency trends, 3.2 Multichip packages, 3.15 3.18 Optical interconnects, 3.18 3.21 Roadmap information, 3.21 Single chip packaging, 3.5 3.15 Array type, 3.6 3.13 Ball Grid Array (BGA), 3.10, 3.11 Direct Die Attach (DCA), 3.11 3.15
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Dual-in-line (DIP), 3.6 Leadless Ceramic Chip Carrier (LCCC), 3.6, 3.7 Pad Array Carrier (PAC), 3.8 3.11 Pin Grid Array (PGA), 3.8 3.11 Plastic Quad Flat Package (PQFP), 3.7, 3.8 Single versus Multichip, 3.15, 3.16 Sequential build-up, material choices for, 11.7, 11.8 Shearing, 35.3, 35.4 Signal integrity, 15.1 15.9 Analog, 15.2, 15.3 Current leakage, 15.5, 15.6 Designing for, 15.4, 15.5 Digital, 15.3 Grounding, 15.6 15.9 Isolation, 15.2 Leakage voltage, 15.5, 15.6 Thermal Electromotive force, 15.2, 15.3 Voltage distribution, 15.6 15.9 Silver, immersion 32.7, 32.8 Single-in-line Package (SIP), 3.15, 3.16 Single-sided boards, 5.6, 5.7 SLC, 22.4, 23.4 23.7 Solder, 45.2 45.11 Alloy candidates, 45.5 45.11 Corrosion, 45.4, 45.5 Lead-free, 45.5 45.11 Properties of, 45.2 Tin-lead (Sn-Pb), 45.3, 47.4 Understanding, 45.1, 45.2 See also Lead-free Solder (tin-lead) plating, 29.15 29.20 Corrective actions, 29.19 Operation, 29.18 Solder bump, 3.22, 3.23 Solder joint reliability, 59.1 59.35 Examples, 59.17 59.20 Experimental tests, 59.1, 59.2 Finite element analysis (FEA), 59.27 59.35 Lead-free impact, 59.2, 59.3, 59.13 59.16, 59.22 59.24, 59.26 Materials properties, 59.7 59.10 Mechanical reliability, 59.20 59.25 Miner s rule, 59.17 Norris-Landsburg accelerator transformation, 59.10 59.14 Power and minicycles, 59.16, 59.17 Shock testing, 59.25 Temperature cycling, 59.3 59.6 Thermal shock, 59.6 Thermomechanical, 59.3 59.20 Weibull distribution, 59.6, 59.7 Solder Mask Over Bare Copper (SMOBC), 33.1 33.24 Solder materials Lead-free solders, 45.3, 45 4 Pastes, 40.24, 40.26 40.30 Tin/lead alloys, 45.3 45 10 Solder mask, 33.1 33.20 Application of, 33.10, 33.11 Assembly considerations, 33.7 Circuitry density, 33.6, 33.7 Conformal coating issues, 33.7, 33.8
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